From: guoren@kernel.org
To: palmer@rivosinc.com, heiko@sntech.de, hch@infradead.org,
arnd@arndb.de, peterz@infradead.org, will@kernel.org,
boqun.feng@gmail.com, longman@redhat.com, mingo@redhat.com,
philipp.tomsich@vrull.eu, cmuellner@linux.com,
linux-kernel@vger.kernel.org, David.Laight@ACULAB.COM
Cc: linux-riscv@lists.infradead.org, linux-csky@vger.kernel.org,
Guo Ren <guoren@linux.alibaba.com>, Guo Ren <guoren@kernel.org>
Subject: [PATCH V8 06/10] riscv: atomic: Clean up unnecessary acquire and release definitions
Date: Sun, 24 Jul 2022 08:25:13 -0400 [thread overview]
Message-ID: <20220724122517.1019187-7-guoren@kernel.org> (raw)
In-Reply-To: <20220724122517.1019187-1-guoren@kernel.org>
From: Guo Ren <guoren@linux.alibaba.com>
Clean up unnecessary xchg_acquire, xchg_release, and cmpxchg_release
custom definitions, because the generic implementation is the same as
the riscv custom implementation.
Before the patch:
000000000000024e <.LBB238>:
ops = xchg_acquire(pending_ipis, 0);
24e: 089937af amoswap.d a5,s1,(s2)
252: 0230000f fence r,rw
0000000000000256 <.LBB243>:
ops = xchg_release(pending_ipis, 0);
256: 0310000f fence rw,w
25a: 089934af amoswap.d s1,s1,(s2)
After the patch:
000000000000026e <.LBB245>:
ops = xchg_acquire(pending_ipis, 0);
26e: 089937af amoswap.d a5,s1,(s2)
0000000000000272 <.LBE247>:
272: 0230000f fence r,rw
0000000000000276 <.LBB249>:
ops = xchg_release(pending_ipis, 0);
276: 0310000f fence rw,w
000000000000027a <.LBB251>:
27a: 089934af amoswap.d s1,s1,(s2)
Only cmpxchg_acquire is necessary (It prevents unnecessary acquire
ordering when the value from lr is different from old).
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
arch/riscv/include/asm/atomic.h | 19 -----
arch/riscv/include/asm/cmpxchg.h | 116 -------------------------------
2 files changed, 135 deletions(-)
diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h
index 0dfe9d857a76..83636320ba95 100644
--- a/arch/riscv/include/asm/atomic.h
+++ b/arch/riscv/include/asm/atomic.h
@@ -249,16 +249,6 @@ c_t arch_atomic##prefix##_xchg_relaxed(atomic##prefix##_t *v, c_t n) \
return __xchg_relaxed(&(v->counter), n, size); \
} \
static __always_inline \
-c_t arch_atomic##prefix##_xchg_acquire(atomic##prefix##_t *v, c_t n) \
-{ \
- return __xchg_acquire(&(v->counter), n, size); \
-} \
-static __always_inline \
-c_t arch_atomic##prefix##_xchg_release(atomic##prefix##_t *v, c_t n) \
-{ \
- return __xchg_release(&(v->counter), n, size); \
-} \
-static __always_inline \
c_t arch_atomic##prefix##_xchg(atomic##prefix##_t *v, c_t n) \
{ \
return __xchg(&(v->counter), n, size); \
@@ -276,12 +266,6 @@ c_t arch_atomic##prefix##_cmpxchg_acquire(atomic##prefix##_t *v, \
return __cmpxchg_acquire(&(v->counter), o, n, size); \
} \
static __always_inline \
-c_t arch_atomic##prefix##_cmpxchg_release(atomic##prefix##_t *v, \
- c_t o, c_t n) \
-{ \
- return __cmpxchg_release(&(v->counter), o, n, size); \
-} \
-static __always_inline \
c_t arch_atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \
{ \
return __cmpxchg(&(v->counter), o, n, size); \
@@ -299,12 +283,9 @@ c_t arch_atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \
ATOMIC_OPS()
#define arch_atomic_xchg_relaxed arch_atomic_xchg_relaxed
-#define arch_atomic_xchg_acquire arch_atomic_xchg_acquire
-#define arch_atomic_xchg_release arch_atomic_xchg_release
#define arch_atomic_xchg arch_atomic_xchg
#define arch_atomic_cmpxchg_relaxed arch_atomic_cmpxchg_relaxed
#define arch_atomic_cmpxchg_acquire arch_atomic_cmpxchg_acquire
-#define arch_atomic_cmpxchg_release arch_atomic_cmpxchg_release
#define arch_atomic_cmpxchg arch_atomic_cmpxchg
#undef ATOMIC_OPS
diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
index 12debce235e5..67ab6375b650 100644
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@ -44,76 +44,6 @@
_x_, sizeof(*(ptr))); \
})
-#define __xchg_acquire(ptr, new, size) \
-({ \
- __typeof__(ptr) __ptr = (ptr); \
- __typeof__(new) __new = (new); \
- __typeof__(*(ptr)) __ret; \
- switch (size) { \
- case 4: \
- __asm__ __volatile__ ( \
- " amoswap.w %0, %2, %1\n" \
- RISCV_ACQUIRE_BARRIER \
- : "=r" (__ret), "+A" (*__ptr) \
- : "r" (__new) \
- : "memory"); \
- break; \
- case 8: \
- __asm__ __volatile__ ( \
- " amoswap.d %0, %2, %1\n" \
- RISCV_ACQUIRE_BARRIER \
- : "=r" (__ret), "+A" (*__ptr) \
- : "r" (__new) \
- : "memory"); \
- break; \
- default: \
- BUILD_BUG(); \
- } \
- __ret; \
-})
-
-#define arch_xchg_acquire(ptr, x) \
-({ \
- __typeof__(*(ptr)) _x_ = (x); \
- (__typeof__(*(ptr))) __xchg_acquire((ptr), \
- _x_, sizeof(*(ptr))); \
-})
-
-#define __xchg_release(ptr, new, size) \
-({ \
- __typeof__(ptr) __ptr = (ptr); \
- __typeof__(new) __new = (new); \
- __typeof__(*(ptr)) __ret; \
- switch (size) { \
- case 4: \
- __asm__ __volatile__ ( \
- RISCV_RELEASE_BARRIER \
- " amoswap.w %0, %2, %1\n" \
- : "=r" (__ret), "+A" (*__ptr) \
- : "r" (__new) \
- : "memory"); \
- break; \
- case 8: \
- __asm__ __volatile__ ( \
- RISCV_RELEASE_BARRIER \
- " amoswap.d %0, %2, %1\n" \
- : "=r" (__ret), "+A" (*__ptr) \
- : "r" (__new) \
- : "memory"); \
- break; \
- default: \
- BUILD_BUG(); \
- } \
- __ret; \
-})
-
-#define arch_xchg_release(ptr, x) \
-({ \
- __typeof__(*(ptr)) _x_ = (x); \
- (__typeof__(*(ptr))) __xchg_release((ptr), \
- _x_, sizeof(*(ptr))); \
-})
-
#define __xchg(ptr, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
@@ -253,52 +183,6 @@
_o_, _n_, sizeof(*(ptr))); \
})
-#define __cmpxchg_release(ptr, old, new, size) \
-({ \
- __typeof__(ptr) __ptr = (ptr); \
- __typeof__(*(ptr)) __old = (old); \
- __typeof__(*(ptr)) __new = (new); \
- __typeof__(*(ptr)) __ret; \
- register unsigned int __rc; \
- switch (size) { \
- case 4: \
- __asm__ __volatile__ ( \
- RISCV_RELEASE_BARRIER \
- "0: lr.w %0, %2\n" \
- " bne %0, %z3, 1f\n" \
- " sc.w %1, %z4, %2\n" \
- " bnez %1, 0b\n" \
- "1:\n" \
- : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
- : "rJ" ((long)__old), "rJ" (__new) \
- : "memory"); \
- break; \
- case 8: \
- __asm__ __volatile__ ( \
- RISCV_RELEASE_BARRIER \
- "0: lr.d %0, %2\n" \
- " bne %0, %z3, 1f\n" \
- " sc.d %1, %z4, %2\n" \
- " bnez %1, 0b\n" \
- "1:\n" \
- : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
- : "rJ" (__old), "rJ" (__new) \
- : "memory"); \
- break; \
- default: \
- BUILD_BUG(); \
- } \
- __ret; \
-})
-
-#define arch_cmpxchg_release(ptr, o, n) \
-({ \
- __typeof__(*(ptr)) _o_ = (o); \
- __typeof__(*(ptr)) _n_ = (n); \
- (__typeof__(*(ptr))) __cmpxchg_release((ptr), \
- _o_, _n_, sizeof(*(ptr))); \
-})
-
#define __cmpxchg(ptr, old, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
--
2.36.1
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next prev parent reply other threads:[~2022-07-24 12:26 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-24 12:25 [PATCH V8 00/10] arch: Add qspinlock support with combo style guoren
2022-07-24 12:25 ` [PATCH V8 01/10] asm-generic: ticket-lock: Remove unnecessary atomic_read guoren
2022-07-24 12:25 ` [PATCH V8 02/10] asm-generic: ticket-lock: Use the same struct definitions with qspinlock guoren
2022-07-27 19:20 ` kernel test robot
2022-07-24 12:25 ` [PATCH V8 03/10] asm-generic: ticket-lock: Move into ticket_spinlock.h guoren
2022-07-24 12:25 ` [PATCH V8 04/10] asm-generic: spinlock: Add queued spinlock support in common header guoren
2022-07-24 12:25 ` [PATCH V8 05/10] riscv: Enable ARCH_INLINE_READ*/WRITE*/SPIN* guoren
2022-07-24 12:25 ` guoren [this message]
2022-07-24 12:25 ` [PATCH V8 07/10] riscv: Add qspinlock support guoren
2022-07-28 0:04 ` kernel test robot
2022-07-28 3:35 ` Guo Ren
2022-07-28 8:14 ` Arnd Bergmann
2022-07-28 8:34 ` Guo Ren
2022-07-24 12:25 ` [PATCH V8 08/10] riscv: Add combo spinlock support guoren
2022-07-24 12:25 ` [PATCH V8 09/10] csky: Enable ARCH_INLINE_READ*/WRITE*/SPIN* guoren
2022-07-24 12:25 ` [PATCH V8 10/10] csky: Add qspinlock support guoren
2022-07-25 2:08 ` Waiman Long
2022-07-25 2:30 ` Guo Ren
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