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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sat, Jul 23, 2022 at 11:22:01AM +0000, Conor.Dooley@microchip.com wrote: > On 15/07/2022 18:51, Conor Dooley wrote: > > From: Conor Dooley > > > > Hey all, > > It's my first time messing around with arch/ code at all, let alone > > more than one arch, so forgive me if I have screwed up how to do a > > migration like this. > > > > The goal here is the fix the incorrectly reported arch topology on > > RISC-V which seems to have been broken since it was added. > > cpu, package and thread IDs are all currently reported as -1, so tools > > like lstopo think systems have multiple threads on the same core when > > this is not true: > > https://github.com/open-mpi/hwloc/issues/536 > > Hey, > > Not got any feedback on the smpboot changes from the RISC-V side. > I tested it on polarfire, the d1 (with both SMP & !SMP set iirc) > & on the u540. It all looked good to me. > > I'd like to have this fixed for v5.20, but there isn't too much > time left before the mw. Not too sure about the cross-tree changes, > does it need an immutable branch or could it go through driver-core? > Catalin suggested removing the CC stable from patch 1/2 & adding it > as a dependency for the 2/2 patch - but obviously that's up to the > committer to sort out. I'm finalising the arm64 queue today, so I don't really want to pull in additional changes beyond critical fixes at this point, I'm afraid. I was half-expecting a pull request from the riscv side last week but I didn't see anything. FWIW, if there's still no movement by -rc1, then I'm happy to queue all of this on its own branch in the arm64 tree for 5.21. Let me know. Will _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv