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From: Conor Dooley <mail@conchuod.ie>
To: Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
	Anup Patel <anup@brainfault.org>,
	Conor Dooley <conor.dooley@microchip.com>,
	Guo Ren <guoren@kernel.org>, Sagar Kadam <sagar.kadam@sifive.com>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org,
	Rob Herring <robh@kernel.org>
Subject: [PATCH 2/3] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible
Date: Fri,  5 Aug 2022 17:28:44 +0100	[thread overview]
Message-ID: <20220805162844.1554247-3-mail@conchuod.ie> (raw)
In-Reply-To: <20220805162844.1554247-1-mail@conchuod.ie>

From: Conor Dooley <conor.dooley@microchip.com>

While "real" hardware might not use the compatible string "riscv,plic0"
it is present in the driver & QEMU uses it for automatically generated
virt machine dtbs. To avoid dt-validate problems with QEMU produced
dtbs, such as the following, add it to the binding.

riscv-virt.dtb: plic@c000000: compatible: 'oneOf' conditional failed, one must be fixed:
        'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'starfive,jh7100-plic', 'canaan,k210-plic']
        'sifive,plic-1.0.0' is not one of ['allwinner,sun20i-d1-plic']
        'sifive,plic-1.0.0' was expected
        'thead,c900-plic' was expected
riscv-virt.dtb: plic@c000000: '#address-cells' is a required property

Reported-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml     | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 92e0f8c3eff2..eb07c4f1a201 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -66,6 +66,11 @@ properties:
           - enum:
               - allwinner,sun20i-d1-plic
           - const: thead,c900-plic
+      - items:
+          - const: sifive,plic-1.0.0
+          - const: riscv,plic0
+        deprecated: true
+        description: For legacy systems & the qemu virt machine only
 
   reg:
     maxItems: 1
-- 
2.37.1


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  parent reply	other threads:[~2022-08-05 16:29 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-05 16:28 [PATCH 0/3] Fix dt-validate issues on qemu dtbdumps due to dt-bindings Conor Dooley
2022-08-05 16:28 ` [PATCH 1/3] dt-bindings: timer: sifive,clint: add legacy riscv compatible Conor Dooley
2022-08-09 14:16   ` Rob Herring
2022-08-09 17:30     ` Conor.Dooley
2022-08-05 16:28 ` Conor Dooley [this message]
2022-08-05 16:28 ` [PATCH 3/3] dt-bindings: riscv: add new riscv,isa strings for emulators Conor Dooley
2022-08-08 21:34 ` [PATCH 0/3] Fix dt-validate issues on qemu dtbdumps due to dt-bindings Jessica Clarke
2022-08-08 22:01   ` Conor.Dooley
2022-08-09 14:14     ` Rob Herring
2022-08-09 17:25       ` Conor.Dooley
2022-08-09 18:36       ` Conor.Dooley
2022-08-15 19:18         ` Conor.Dooley
2022-08-16 14:06           ` Andrew Jones
2022-08-16 22:53             ` Conor.Dooley
2022-08-17  7:52               ` Andrew Jones

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