From: Conor Dooley <conor.dooley@microchip.com>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
Shravan Chippa <shravan.chippa@microchip.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Cyril Jean <Cyril.Jean@microchip.com>,
Lewis Hanly <lewis.hanly@microchip.com>,
Vattipalli Praveen <praveen.kumar@microchip.com>,
Wolfgang Grandegger <wg@aries-embedded.de>,
<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH 6/9] riscv: dts: microchip: icicle: update pci address properties
Date: Fri, 26 Aug 2022 15:28:04 +0100 [thread overview]
Message-ID: <20220826142806.3658434-7-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220826142806.3658434-1-conor.dooley@microchip.com>
For the v2022.09 reference design the PCI root port's data region has
been moved to FIC1 from FIC0. This is a shorter path, allowing for
higher clock rates and improved through-put. As a result, the address at
which the PCIe's data region appears to the core complex has changed.
The config region's address is unchanged.
As FIC0 is no longer used, its clock can be removed too.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index a21440c8ee03..32d51c4a5b0c 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -2,6 +2,7 @@
/* Copyright (c) 2020-2021 Microchip Technology Inc */
/ {
+
compatible = "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpfs-icicle-kit",
"microchip,mpfs";
@@ -38,13 +39,13 @@ fabric_clk1: fabric-clk1 {
clock-frequency = <125000000>;
};
- pcie: pcie@2000000000 {
+ pcie: pcie@3000000000 {
compatible = "microchip,pcie-host-1.0";
#address-cells = <0x3>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
device_type = "pci";
- reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+ reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
reg-names = "cfg", "apb";
bus-range = <0x0 0x7f>;
interrupt-parent = <&plic>;
@@ -54,9 +55,9 @@ pcie: pcie@2000000000 {
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
interrupt-map-mask = <0 0 0 7>;
- clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
- clock-names = "fic0", "fic1", "fic3";
- ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+ clocks = <&fabric_clk1>, <&fabric_clk3>;
+ clock-names = "fic1", "fic3";
+ ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
msi-parent = <&pcie>;
msi-controller;
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-08-26 14:29 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-26 14:27 [PATCH 0/9] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
2022-08-26 14:27 ` [PATCH 1/9] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
2022-08-27 9:21 ` Krzysztof Kozlowski
2022-08-26 14:28 ` [PATCH 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp Conor Dooley
2022-08-27 9:22 ` Krzysztof Kozlowski
2022-08-26 14:28 ` [PATCH 3/9] dt-bindings: riscv: microchip: document the sev kit Conor Dooley
2022-08-27 9:23 ` Krzysztof Kozlowski
2022-08-26 14:28 ` [PATCH 4/9] riscv: dts: microchip: add pci dma ranges for the icicle kit Conor Dooley
2022-08-26 14:28 ` [PATCH 5/9] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi Conor Dooley
2022-08-26 14:28 ` Conor Dooley [this message]
2022-08-26 14:28 ` [PATCH 7/9] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses Conor Dooley
2022-08-26 14:28 ` [PATCH 8/9] riscv: dts: microchip: add sevkit device tree Conor Dooley
2022-08-26 14:28 ` [PATCH 9/9] riscv: dts: microchip: add a devicetree for aries' m100pfsevp Conor Dooley
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220826142806.3658434-7-conor.dooley@microchip.com \
--to=conor.dooley@microchip.com \
--cc=Cyril.Jean@microchip.com \
--cc=aou@eecs.berkeley.edu \
--cc=daire.mcnamara@microchip.com \
--cc=devicetree@vger.kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=lewis.hanly@microchip.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=praveen.kumar@microchip.com \
--cc=robh+dt@kernel.org \
--cc=shravan.chippa@microchip.com \
--cc=wg@aries-embedded.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).