From: Palmer Dabbelt <palmer@rivosinc.com>
To: linux-riscv@lists.infradead.org
Cc: Palmer Dabbelt <palmer@rivosinc.com>
Subject: [PATCH] RISC-V: Add support for Ztso
Date: Thu, 1 Sep 2022 20:43:52 -0700 [thread overview]
Message-ID: <20220902034352.8825-1-palmer@rivosinc.com> (raw)
The Ztso extension was recently frozen, this adds support for running
binaries that depend on TSO on systems that support Ztso.
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
This is very minimaly tested: I can run no-Ztso binaries on both
yes-Ztso and no-Ztso QEMU instances, but I don't have a yes-Ztso
userspace together in order to make sure that works.
---
arch/riscv/include/asm/elf.h | 18 ++++++++++++++++--
arch/riscv/include/asm/hwcap.h | 3 +++
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 3 +++
4 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h
index 14fc7342490b..7a17d2275b76 100644
--- a/arch/riscv/include/asm/elf.h
+++ b/arch/riscv/include/asm/elf.h
@@ -14,6 +14,7 @@
#include <asm/auxvec.h>
#include <asm/byteorder.h>
#include <asm/cacheinfo.h>
+#include <asm/hwcap.h>
/*
* These are used to set parameters in the core dumps.
@@ -31,10 +32,23 @@
#define ELF_DATA ELFDATA2LSB
/*
- * This is used to ensure we don't load something for the wrong architecture.
+ * Binaries that assume TSO cannot be correctly run on non-TSO systems, so
+ * prevent them from even being loaded.
+ */
+#define EF_RISCV_TSO 0x0010
+
+static inline int riscv_elf_tso_ok(long eflags)
+{
+ return likely(!(eflags & EF_RISCV_TSO)) || riscv_tso_hw;
+}
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture or
+ * variant.
*/
#define elf_check_arch(x) (((x)->e_machine == EM_RISCV) && \
- ((x)->e_ident[EI_CLASS] == ELF_CLASS))
+ ((x)->e_ident[EI_CLASS] == ELF_CLASS) && \
+ riscv_elf_tso_ok((x)->e_flags))
extern bool compat_elf_check_arch(Elf32_Ehdr *hdr);
#define compat_elf_check_arch compat_elf_check_arch
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 6f59ec64175e..4e1d94c43d51 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -36,6 +36,8 @@ extern unsigned long elf_hwcap;
#define RISCV_ISA_EXT_s ('s' - 'a')
#define RISCV_ISA_EXT_u ('u' - 'a')
+extern bool riscv_tso_hw;
+
/*
* Increse this to higher value as kernel support more ISA extensions.
*/
@@ -58,6 +60,7 @@ enum riscv_isa_ext_id {
RISCV_ISA_EXT_ZICBOM,
RISCV_ISA_EXT_ZIHINTPAUSE,
RISCV_ISA_EXT_SSTC,
+ RISCV_ISA_EXT_ZTSO,
RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 0be8a2403212..d8371c249cc8 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -95,6 +95,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
+ __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
};
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 3b5583db9d80..b8ab2b0a9e78 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -25,6 +25,8 @@
unsigned long elf_hwcap __read_mostly;
+bool riscv_tso_hw __read_mostly;
+
/* Host ISA bitmap */
static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
@@ -204,6 +206,7 @@ void __init riscv_fill_hwcap(void)
SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
+ SET_ISA_EXT_MAP("ztso", RISCV_ISA_EXT_ZTSO);
}
#undef SET_ISA_EXT_MAP
}
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next reply other threads:[~2022-09-02 3:47 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-02 3:43 Palmer Dabbelt [this message]
2022-09-02 6:39 ` [PATCH] RISC-V: Add support for Ztso Andreas Schwab
2022-09-16 14:09 ` Palmer Dabbelt
2022-09-02 6:50 ` Anup Patel
2022-09-16 14:15 ` Palmer Dabbelt
2022-09-16 10:00 ` Conor.Dooley
2022-09-16 14:09 ` Palmer Dabbelt
2022-09-16 14:13 ` Conor.Dooley
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220902034352.8825-1-palmer@rivosinc.com \
--to=palmer@rivosinc.com \
--cc=linux-riscv@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).