From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF023C433FE for ; Thu, 24 Nov 2022 17:23:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vN+VvYpgNwhqplVqS+1lMft3MKDYrp+AcLg0C+LCVGU=; b=kEOqqvGctYpewh /fb+9C5b3mOFjjx800oAcDjvuR59IOfPx4AeuPFRfcEun7Jk3N0YK6uzeH5XemmWUjirVz8DMRJ5T b0ipP7/Uqz3x5eDfweVPV0TQbx9M7Pqb1h2GDGRfdWCO4pOVOm7aQsEALaPU0zMIyajgZq/DfjAEu ZxatYnDyd5AIqQ87E2NhijOc44h0siF4iLRuapzSC5Y6pljEL6lMi0li/31EephLfZ5fCcgFNbeW1 vfz/L0CyyQ7P8WMDYpyM+bP9j+mTYJB+e9ILpurOREyRDBTOaIbP14u3Z5On8I46pWcua1dMjRnGq MlJH1/JXKCNfBL26WyqQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oyFwQ-00AR2L-Sg; Thu, 24 Nov 2022 17:23:14 +0000 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oyFvy-00AQhp-7I for linux-riscv@lists.infradead.org; Thu, 24 Nov 2022 17:22:48 +0000 Received: by mail-wr1-x42b.google.com with SMTP id z4so3378221wrr.3 for ; Thu, 24 Nov 2022 09:22:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mTqb56t1MZLGmiNAO1wdyZdWaJfReceiuidXqQh2rDM=; b=KfjvVurbEEHmImk+BeMXSlP/P01FDdtROFgje3lqyafzq1l4MuAk6zvv+z0YWgWo8Y qYtq3m1dI5DLDLUhoIAXE4e40Dfv2h6UmmZZU+c9o3uzw3jimtlE3ocNBBIzu2XMsuNf 5oaqcqjMKECmp3a9HfSnJnclz1sS2ubq5lTZCrvBzQUbVYX3KgeDGrzYN839iPz51ZAW XHYcU5mbzwp31XiQ1LaQCsQ48eNgQMZKh70IrmqpXpjOOP93zVno0PXYRuZamL0/xa/a sLr/GDKp3xezK69+wlRTlS3BAE/3cGvl3PzSmE+ff2q/LJZdJwtkCSnrZocWN/IEyESl s/Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mTqb56t1MZLGmiNAO1wdyZdWaJfReceiuidXqQh2rDM=; b=RPonHDRuH7CCuQmcd6A9iKZkL7rj3hEdV9ZgBLfOjQ9FDPN0Aw4T1MJv5LcA26aBvI I4E7u0zDt82bzLgRe9ciDzVS3O0khWC3OKvS6RkMjX/03rtf3r1L92XtDlGniTb4KesC 86jecKpnEGHIq29dlM4c87UYDUUiyCDU0s1pbmYdZ4kXzAPZ6w2hgV49psMl/eC+L7FG J3fnwxHPY6w65aKYO68xXvjDwtqysx0hL79Rwr98d5d5fnnnAgQiAV+wSr6aLdgFHAOw ZGmF6oaHdoOypiUYDE6+tAxy+FgXk8FRPcSEej0sz5wB5mgRrtcQlb1rdb+iqY3qEukU Pjfw== X-Gm-Message-State: ANoB5plrsjDYTj2aAokGNi/oieNrthlobLEizqJRUWBSNGwa4IzrIuDi 4QhmwqKYtwS+rNrQmeN4piM= X-Google-Smtp-Source: AA0mqf57Qf4xEDouq8EP9JiPsPwdGe9ZW24Iy8vCM2dBBoxAkEPGGF7rQ7z12eOZeKURbyRZNPForA== X-Received: by 2002:adf:ff89:0:b0:22e:38b:95ff with SMTP id j9-20020adfff89000000b0022e038b95ffmr10650363wrr.202.1669310562597; Thu, 24 Nov 2022 09:22:42 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2501:c701:89ee:3f5d:1c99:35d8]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c445100b003c64c186206sm2698086wmn.16.2022.11.24.09.22.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Nov 2022 09:22:41 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Guo Ren Cc: Jisheng Zhang , Atish Patra , Anup Patel , Andrew Jones , Nathan Chancellor , Philipp Tomsich , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v4 3/7] riscv: errata: Add Andes alternative ports Date: Thu, 24 Nov 2022 17:22:03 +0000 Message-Id: <20221124172207.153718-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221124172207.153718-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221124172207.153718-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221124_092246_319298_0B932A07 X-CRM114-Status: GOOD ( 19.94 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Lad Prabhakar Add required ports of the Alternative scheme for Andes CPU cores. Signed-off-by: Lad Prabhakar --- RFC v3 -> v4 * New patch --- arch/riscv/Kconfig.erratas | 22 +++++++++ arch/riscv/errata/Makefile | 1 + arch/riscv/errata/andes/Makefile | 1 + arch/riscv/errata/andes/errata.c | 68 ++++++++++++++++++++++++++++ arch/riscv/include/asm/alternative.h | 3 ++ arch/riscv/include/asm/errata_list.h | 5 ++ arch/riscv/kernel/alternative.c | 5 ++ 7 files changed, 105 insertions(+) create mode 100644 arch/riscv/errata/andes/Makefile create mode 100644 arch/riscv/errata/andes/errata.c diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas index 69621ae6d647..74b44e5dd710 100644 --- a/arch/riscv/Kconfig.erratas +++ b/arch/riscv/Kconfig.erratas @@ -1,5 +1,27 @@ menu "CPU errata selection" +config ERRATA_ANDES + bool "Andes AX45MP errata" + depends on !XIP_KERNEL + select RISCV_ALTERNATIVE + help + All Andes errata Kconfig depend on this Kconfig. Disabling + this Kconfig will disable all Andes errata. Please say "Y" + here if your platform uses Andes CPU cores. + + Otherwise, please say "N" here to avoid unnecessary overhead. + +config ERRATA_ANDES_CMO + bool "Apply Andes cache management errata" + depends on ERRATA_ANDES && MMU + select RISCV_DMA_NONCOHERENT + default y + help + This will apply the cache management errata to handle the + non-standard handling on non-coherent operations on Andes cores. + + If you don't know what to do here, say "Y". + config ERRATA_SIFIVE bool "SiFive errata" depends on !XIP_KERNEL diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile index a1055965fbee..81828e80f6dc 100644 --- a/arch/riscv/errata/Makefile +++ b/arch/riscv/errata/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_ERRATA_SIFIVE) += sifive/ obj-$(CONFIG_ERRATA_THEAD) += thead/ +obj-$(CONFIG_ERRATA_ANDES) += andes/ diff --git a/arch/riscv/errata/andes/Makefile b/arch/riscv/errata/andes/Makefile new file mode 100644 index 000000000000..2d644e19caef --- /dev/null +++ b/arch/riscv/errata/andes/Makefile @@ -0,0 +1 @@ +obj-y += errata.o diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c new file mode 100644 index 000000000000..ec3e052ca8c7 --- /dev/null +++ b/arch/riscv/errata/andes/errata.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Erratas to be applied for Andes CPU cores + * + * Copyright (C) 2022 Renesas Electronics Corporation. + * + * Author: Lad Prabhakar + */ + +#include +#include + +#include +#include +#include +#include +#include + +static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigned long impid) +{ + if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO)) + return false; + + if (arch_id != 0x8000000000008a45 || impid != 0x500) + return false; + + riscv_cbom_block_size = 1; + riscv_noncoherent_supported(); + + return true; +} + +static u32 andes_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid) +{ + u32 cpu_req_errata = 0; + + if (errata_probe_iocp(stage, archid, impid)) + cpu_req_errata |= BIT(ERRATA_ANDESTECH_NO_IOCP); + + return cpu_req_errata; +} + +void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage) +{ + u32 cpu_req_errata = andes_errata_probe(stage, archid, impid); + struct alt_entry *alt; + u32 tmp; + + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) + return; + + for (alt = begin; alt < end; alt++) { + if (alt->vendor_id != ANDESTECH_VENDOR_ID) + continue; + if (alt->errata_id >= ERRATA_ANDESTECH_NUMBER) + continue; + + tmp = (1U << alt->errata_id); + if (cpu_req_errata & tmp) { + patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); + + riscv_alternative_fix_auipc_jalr(alt->old_ptr, alt->alt_len, + alt->old_ptr - alt->alt_ptr); + } + } +} diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h index 6511dd73e812..d8012af30cbd 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -46,6 +46,9 @@ void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, void thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned long archid, unsigned long impid, unsigned int stage); +void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage); void riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned int stage); diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 4180312d2a70..2ba7e6e74540 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -9,6 +9,11 @@ #include #include +#ifdef CONFIG_ERRATA_ANDES +#define ERRATA_ANDESTECH_NO_IOCP 0 +#define ERRATA_ANDESTECH_NUMBER 1 +#endif + #ifdef CONFIG_ERRATA_SIFIVE #define ERRATA_SIFIVE_CIP_453 0 #define ERRATA_SIFIVE_CIP_1200 1 diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c index a7d26a00beea..4ded3e9aa3bc 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -47,6 +47,11 @@ static void __init_or_module riscv_fill_cpu_mfr_info(struct cpu_manufacturer_inf case THEAD_VENDOR_ID: cpu_mfr_info->patch_func = thead_errata_patch_func; break; +#endif +#ifdef CONFIG_ERRATA_ANDES + case ANDESTECH_VENDOR_ID: + cpu_mfr_info->patch_func = andes_errata_patch_func; + break; #endif default: cpu_mfr_info->patch_func = NULL; -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv