From: guoren@kernel.org
To: anup@brainfault.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, conor.dooley@microchip.com, heiko@sntech.de,
rostedt@goodmis.org, mhiramat@kernel.org, jolsa@redhat.com,
bp@suse.de, jpoimboe@kernel.org, suagrfillet@gmail.com,
andy.chiu@sifive.com, mark.rutland@arm.com
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Guo Ren <guoren@linux.alibaba.com>, Guo Ren <guoren@kernel.org>
Subject: [PATCH V4 2/7] riscv: ftrace: Remove wasted nops for !RISCV_ISA_C
Date: Mon, 28 Nov 2022 22:32:25 -0500 [thread overview]
Message-ID: <20221129033230.255947-3-guoren@kernel.org> (raw)
In-Reply-To: <20221129033230.255947-1-guoren@kernel.org>
From: Guo Ren <guoren@linux.alibaba.com>
When CONFIG_RISCV_ISA_C=n, -fpatchable-function-entry=8 would generate
more nops than we expect. Because it treat nop opcode as 0x00000013
instead of 0x0001.
Dump of assembler code for function dw_pcie_free_msi:
0xffffffff806fce94 <+0>: sd ra,-8(sp)
0xffffffff806fce98 <+4>: auipc ra,0xff90f
0xffffffff806fce9c <+8>: jalr -684(ra) # 0xffffffff8000bbec
<ftrace_caller>
0xffffffff806fcea0 <+12>: ld ra,-8(sp)
0xffffffff806fcea4 <+16>: nop /* wasted */
0xffffffff806fcea8 <+20>: nop /* wasted */
0xffffffff806fceac <+24>: nop /* wasted */
0xffffffff806fceb0 <+28>: nop /* wasted */
0xffffffff806fceb4 <+0>: addi sp,sp,-48
0xffffffff806fceb8 <+4>: sd s0,32(sp)
0xffffffff806fcebc <+8>: sd s1,24(sp)
0xffffffff806fcec0 <+12>: sd s2,16(sp)
0xffffffff806fcec4 <+16>: sd s3,8(sp)
0xffffffff806fcec8 <+20>: sd ra,40(sp)
0xffffffff806fcecc <+24>: addi s0,sp,48
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
arch/riscv/Makefile | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 1c8ec656e916..36cc609c5d03 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -11,7 +11,11 @@ LDFLAGS_vmlinux :=
ifeq ($(CONFIG_DYNAMIC_FTRACE),y)
LDFLAGS_vmlinux := --no-relax
KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY
+ifeq ($(CONFIG_RISCV_ISA_C),y)
CC_FLAGS_FTRACE := -fpatchable-function-entry=8
+else
+ CC_FLAGS_FTRACE := -fpatchable-function-entry=4
+endif
endif
ifeq ($(CONFIG_CMODEL_MEDLOW),y)
--
2.36.1
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next prev parent reply other threads:[~2022-11-29 3:33 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-29 3:32 [PATCH V4 0/7] riscv: ftrace: Fixup ftrace detour code & Optimization guoren
2022-11-29 3:32 ` [PATCH V4 1/7] riscv: ftrace: Fixup panic by disabling preemption guoren
2022-11-29 3:32 ` guoren [this message]
2022-11-29 3:32 ` [PATCH V4 3/7] riscv: ftrace: Reduce the detour code size to half guoren
2022-11-29 3:32 ` [PATCH V4 4/7] riscv: ftrace: Add ftrace_graph_func guoren
2022-11-29 3:32 ` [PATCH V4 5/7] riscv: ftrace: Make ftrace_caller call ftrace_graph_func guoren
2022-11-29 3:32 ` [PATCH V4 6/7] riscv: ftrace: Add DYNAMIC_FTRACE_WITH_DIRECT_CALLS support guoren
2022-11-29 12:03 ` Song Shuai
2022-11-30 7:29 ` Guo Ren
2022-12-01 20:02 ` Conor Dooley
2022-12-01 20:06 ` Palmer Dabbelt
2022-12-01 20:15 ` Conor Dooley
2022-11-29 3:32 ` [PATCH V4 7/7] samples: ftrace: Add riscv support for SAMPLE_FTRACE_DIRECT[_MULTI] guoren
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