From: Conor Dooley <conor@kernel.org>
To: Xu Yilun <yilun.xu@intel.com>, conor@kernel.org
Cc: Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Moritz Fischer <mdf@kernel.org>, Wu Hao <hao.wu@intel.com>,
Tom Rix <trix@redhat.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org
Subject: [PATCH v1 2/6] dt-bindings: soc: microchip: add a property for system controller flash
Date: Fri, 17 Feb 2023 16:40:19 +0000 [thread overview]
Message-ID: <20230217164023.14255-3-conor@kernel.org> (raw)
In-Reply-To: <20230217164023.14255-1-conor@kernel.org>
From: Conor Dooley <conor.dooley@microchip.com>
The system controller "shares" a SPI flash device with a QSPI controller
in the MSS. This flash is used to store FPGA bitstreams & other
metadata. IAP and Auto Upgrade both write images to this flash that the
System Controller will use to re-program the FPGA.
Add a phandle property signifying which flash device is connected to the
system controller.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../soc/microchip/microchip,mpfs-sys-controller.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
index 04ffee3a7c59..97a7cb74cbf9 100644
--- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
@@ -26,6 +26,16 @@ properties:
compatible:
const: microchip,mpfs-sys-controller
+ microchip,bitstream-flash:
+ $ref: "/schemas/types.yaml#/definitions/phandle"
+ description:
+ The SPI flash connected to the system controller's QSPI controller.
+ The system controller may retrieve FPGA bitstreams from this flash to
+ perform In-Application Programming (IAP) or during device initialisation
+ for Auto Update. The MSS and system controller have separate QSPI
+ controllers and this flash is connected to both. Software running in the
+ MSS can write bitstreams to the flash.
+
required:
- compatible
- mboxes
--
2.39.1
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next prev parent reply other threads:[~2023-02-17 16:41 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-17 16:40 [PATCH v1 0/6] PolarFire SoC Auto Update Support Conor Dooley
2023-02-17 16:40 ` [PATCH v1 1/6] soc: microchip: mpfs: add a prefix to rx_callback() Conor Dooley
2023-02-17 16:40 ` Conor Dooley [this message]
2023-02-26 18:01 ` [PATCH v1 2/6] dt-bindings: soc: microchip: add a property for system controller flash Rob Herring
2023-02-17 16:40 ` [PATCH v1 3/6] soc: microchip: mpfs: enable access to the system controller's flash Conor Dooley
2023-02-17 16:40 ` [PATCH v1 4/6] soc: microchip: mpfs: add auto-update subdev to system controller Conor Dooley
2023-02-17 16:40 ` [PATCH v1 5/6] fpga: add PolarFire SoC Auto Update support Conor Dooley
2023-03-04 16:38 ` Xu Yilun
2023-03-04 17:01 ` Conor Dooley
2023-02-17 16:40 ` [PATCH v1 6/6] riscv: dts: microchip: add the mpfs' system controller qspi & associated flash Conor Dooley
2023-02-24 7:57 ` [PATCH v1 0/6] PolarFire SoC Auto Update Support Xu Yilun
2023-02-24 8:28 ` Conor Dooley
2023-02-27 22:04 ` Russ Weight
2023-02-27 22:16 ` Conor Dooley
2023-02-27 22:42 ` Russ Weight
2023-02-27 22:56 ` Conor Dooley
2023-03-22 18:51 ` Conor Dooley
2023-03-30 0:11 ` Russ Weight
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