From: Wang Chen <unicornxw@gmail.com>
To: linux-riscv@lists.infradead.org, conor@kernel.org,
aou@eecs.berkeley.edu, krzysztof.kozlowski+dt@linaro.org,
palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
jszhang@kernel.org, guoren@kernel.org, chao.wei@sophgo.com,
xiaoguang.xing@sophgo.com, Wang Chen <wangchen20@iscas.ac.cn>
Subject: [PATCH 04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles
Date: Fri, 15 Sep 2023 15:23:33 +0800 [thread overview]
Message-ID: <20230915072333.117991-1-wangchen20@iscas.ac.cn> (raw)
The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C920 core is used in the SOPHGO SG2042 SoC.
Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 38c0b5213736..185a0191bad6 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -47,6 +47,7 @@ properties:
- sifive,u74-mc
- thead,c906
- thead,c910
+ - thead,c920
- const: riscv
- items:
- enum:
--
2.25.1
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next reply other threads:[~2023-09-15 7:23 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-15 7:23 Wang Chen [this message]
2023-09-15 14:11 ` [PATCH 04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles Conor Dooley
2023-09-15 15:03 ` Rob Herring
2023-09-16 0:46 ` Chen Wang
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