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charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200406_221509_246064_2D66EA30 X-CRM114-Status: GOOD ( 12.26 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: anup@brainfault.org, linux-kernel@vger.kernel.org, zong.li@sifive.com, Paul Walmsley , linux-riscv@lists.infradead.org, Christoph Hellwig Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On 4/3/20 11:53 AM, Palmer Dabbelt wrote: > On Sun, 22 Mar 2020 04:00:28 PDT (-0700), alex@ghiti.fr wrote: >> Define precisely the size of the user accessible virtual space size >> for sv32/39/48 mmu types and explain why the whole virtual address >> space is split into 2 equal chunks between kernel and user space. >> >> Signed-off-by: Alexandre Ghiti >> --- >>  arch/riscv/include/asm/pgtable.h | 11 +++++++++-- >>  1 file changed, 9 insertions(+), 2 deletions(-) >> >> diff --git a/arch/riscv/include/asm/pgtable.h >> b/arch/riscv/include/asm/pgtable.h >> index 06361db3f486..be117a0b4ea1 100644 >> --- a/arch/riscv/include/asm/pgtable.h >> +++ b/arch/riscv/include/asm/pgtable.h >> @@ -456,8 +456,15 @@ static inline int ptep_clear_flush_young(struct >> vm_area_struct *vma, >>  #define FIXADDR_START    (FIXADDR_TOP - FIXADDR_SIZE) >> >>  /* >> - * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. >> - * Note that PGDIR_SIZE must evenly divide TASK_SIZE. >> + * Task size is: >> + * -     0x9fc00000 (~2.5GB) for RV32. >> + * -   0x4000000000 ( 256GB) for RV64 using SV39 mmu >> + * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu >> + * >> + * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V >> + * Instruction Set Manual Volume II: Privileged Architecture" states >> that >> + * "load and store effective addresses, which are 64bits, must have bits >> + * 63–48 all equal to bit 47, or else a page-fault exception will >> occur." >>   */ >>  #ifdef CONFIG_64BIT >>  #define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2) > > Reviewed-by: Palmer Dabbelt Thanks, Alex