Re: [PATCH 2/9] riscv: remove dead big endian code

[Nick Kossifidis <mick@ics.forth.gr>]

Στις 2019-04-11 14:56, Christoph Hellwig έγραψε:
> RISC-V is always little endian.
> 
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
>  arch/riscv/include/asm/uaccess.h | 9 +--------
>  1 file changed, 1 insertion(+), 8 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/uaccess.h 
> b/arch/riscv/include/asm/uaccess.h
> index cc5b253d4c57..5c50ed6f8c93 100644
> --- a/arch/riscv/include/asm/uaccess.h
> +++ b/arch/riscv/include/asm/uaccess.h
> @@ -99,15 +99,8 @@ static inline int __access_ok(unsigned long addr,
> unsigned long size)
>   * on our cache or tlb entries.
>   */
> 
> -#if defined(__LITTLE_ENDIAN)
> -#define __MSW	1
>  #define __LSW	0
> -#elif defined(__BIG_ENDIAN)
> -#define __MSW	0
> -#define	__LSW	1
> -#else
> -#error "Unknown endianness"
> -#endif
> +#define __MSW	1
> 
>  /*
>   * The "__xxx" versions of the user access functions do not verify the 
> address

 From the ISA manual:

"We chose little-endian byte ordering for the RISC-V memory system 
because
little-endian systems are currently dominant commercially (all x86 
systems;
iOS, Android, and Windows for ARM). A minor point is that we have also 
found
little-endian memory systems to be more natural for hardware designers.
However, certain application areas, such as IP networking, operate on
big-endian data structures, and certain legacy code bases have been 
built
assuming big-endian processors, so we expect that future specifications 
will
describe big-endian or bi-endian variants of RISC-V."

I don't think we can definitely say that RISC-V will always have a 
little-endian,
memory system only that it is little-endian for now. Also this code acts 
as a check,
I'd prefer if you put an error (something like "unsupported endianess, 
check your
toolchain") in case __BIG_ENDIAN was defined instead of completely 
removing the
check.

Regards,
Nick

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