From: Icenowy Zheng <uwu@icenowy.me>
To: Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Jisheng Zhang <jszhang@kernel.org>,
Samuel Holland <samuel@sholland.org>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH 1/3] dt-bindings: timer: sifive,clint: add comaptibles for T-Head's C9xx
Date: Wed, 07 Dec 2022 18:47:26 +0800 [thread overview]
Message-ID: <34fe4161718e395f5e9890f9358a25f697af9e24.camel@icenowy.me> (raw)
In-Reply-To: <20221121041757.418645-2-uwu@icenowy.me>
在 2022-11-21星期一的 12:17 +0800,Icenowy Zheng写道:
> T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not
> compliant to the newcoming ACLINT spec) because of lack of mtime
> register.
>
> Add a compatible string formatted like the C9xx-specific PLIC
> compatible, and do not allow a SiFive one as fallback because they're
> not really compliant.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Hi, could this patch be picked ASAP? Becuase it will be used then in
further OpenSBI patches to enable proper operation of T-Head timer.
I know the following 2 patches are in doubt and further rework for them
are needed.
> ---
> Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8
> ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git
> a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> index bbad24165837..aada6957216c 100644
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -20,6 +20,10 @@ description:
> property of "/cpus" DT node. The "timebase-frequency" DT property
> is
> described in Documentation/devicetree/bindings/riscv/cpus.yaml
>
> + T-Head C906/C910 CPU cores include an implementation of CLINT too,
> however
> + their implementation lacks a memory-mapped MTIME register, thus
> not
> + compatible with SiFive ones.
> +
> properties:
> compatible:
> oneOf:
> @@ -29,6 +33,10 @@ properties:
> - starfive,jh7100-clint
> - canaan,k210-clint
> - const: sifive,clint0
> + - items:
> + - enum:
> + - allwinner,sun20i-d1-clint
> + - const: thead,c900-clint
> - items:
> - const: sifive,clint0
> - const: riscv,clint0
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next prev parent reply other threads:[~2022-12-07 10:47 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-21 4:17 [PATCH 0/3] Some DT binding quirks for T-Head C9xx Icenowy Zheng
2022-11-21 4:17 ` [PATCH 1/3] dt-bindings: timer: sifive,clint: add comaptibles for T-Head's C9xx Icenowy Zheng
2022-11-21 10:06 ` Krzysztof Kozlowski
2022-11-26 19:39 ` Samuel Holland
2022-11-27 7:25 ` Icenowy Zheng
2022-12-07 10:47 ` Icenowy Zheng [this message]
2022-12-07 11:33 ` Conor Dooley
2022-11-21 4:17 ` [PATCH 2/3] dt-bindings: timer: sifive,clint: add compatible for OpenC906 Icenowy Zheng
2022-11-21 10:06 ` Krzysztof Kozlowski
2022-11-22 7:18 ` Icenowy Zheng
2022-11-22 7:35 ` Krzysztof Kozlowski
2022-11-22 7:41 ` Icenowy Zheng
2022-11-22 8:47 ` Krzysztof Kozlowski
2022-11-30 18:13 ` Rob Herring
2022-12-01 19:18 ` Conor Dooley
2022-12-02 6:12 ` Icenowy Zheng
2022-12-05 10:36 ` Conor Dooley
2022-12-05 11:03 ` Icenowy Zheng
2022-12-05 15:05 ` Conor Dooley
2022-12-05 15:59 ` Icenowy Zheng
2022-12-05 16:54 ` Conor Dooley
2022-12-06 3:46 ` Icenowy Zheng
2022-12-06 6:33 ` Conor Dooley
2022-11-21 4:17 ` [PATCH 3/3] dt-bindings: interrupt-controller: sifive,plic: add OpenC906 compatible Icenowy Zheng
2022-11-21 10:06 ` Krzysztof Kozlowski
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