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[78.26.46.173]) by smtp.gmail.com with ESMTPSA id b14-20020a2eb90e000000b0025dda2c8013sm3912287ljb.28.2022.07.27.05.07.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Jul 2022 05:07:51 -0700 (PDT) Message-ID: <372e37bf-ac90-c371-ad9e-b9c18e1cc059@linaro.org> Date: Wed, 27 Jul 2022 14:07:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH v2 1/2] dt-bindings: riscv: Add optional DT property riscv,timer-can-wake-cpu Content-Language: en-US To: Anup Patel , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Andrew Jones , Atish Patra , Samuel Holland , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20220727114302.302201-1-apatel@ventanamicro.com> <20220727114302.302201-2-apatel@ventanamicro.com> From: Krzysztof Kozlowski In-Reply-To: <20220727114302.302201-2-apatel@ventanamicro.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220727_050755_520317_A47CDD87 X-CRM114-Status: GOOD ( 15.29 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 27/07/2022 13:43, Anup Patel wrote: > We add an optional DT property riscv,timer-can-wake-cpu which if present > in CPU DT node then CPU timer is always powered-on and never loses context. > > Signed-off-by: Anup Patel > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index d632ac76532e..b60b64b4113a 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -78,6 +78,12 @@ properties: > - rv64imac > - rv64imafdc > > + riscv,timer-can-wake-cpu: > + type: boolean > + description: > + If present, the timer interrupt can wake up the CPU from > + suspend/idle state. Isn't this a property of a timer, not CPU? IOW, your timer node should have "wakeup-source" property. Now that's actual problem: why the RISC-V timer is bound to "riscv" compatible, not to dedicated timer node? How is it related to actual CPU (not SoC)? Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv