From: Nick Hu <nickhu@andestech.com>
To: <greentime@andestech.com>, <palmer@sifive.com>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Cc: green.hu@gmail.com, Nick Hu <nickhu@andestech.com>
Subject: [PATCH] riscv: Fix udelay in RV32.
Date: Tue, 28 May 2019 17:26:49 +0800 [thread overview]
Message-ID: <381ee6950c84b868ca6a3c676eb981a1980889a3.1559035050.git.nickhu@andestech.com> (raw)
In RV32, udelay would delay the wrong cycle.
When it shifts right "UDELAY_SHITFT" bits, it
either delays 0 cycle or 1 cycle. It only works
correctly in RV64. Because the 'ucycles' always
needs to be 64 bits variable.
Signed-off-by: Nick Hu <nickhu@andestech.com>
---
arch/riscv/lib/delay.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/lib/delay.c b/arch/riscv/lib/delay.c
index dce8ae24c6d3..da847f49fb74 100644
--- a/arch/riscv/lib/delay.c
+++ b/arch/riscv/lib/delay.c
@@ -88,7 +88,7 @@ EXPORT_SYMBOL(__delay);
void udelay(unsigned long usecs)
{
- unsigned long ucycles = usecs * lpj_fine * UDELAY_MULT;
+ unsigned long long ucycles = (unsigned long long)usecs * lpj_fine * UDELAY_MULT;
if (unlikely(usecs > MAX_UDELAY_US)) {
__delay((u64)usecs * riscv_timebase / 1000000ULL);
--
2.17.0
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next reply other threads:[~2019-05-28 9:27 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-28 9:26 Nick Hu [this message]
2019-05-30 4:09 ` [PATCH] riscv: Fix udelay in RV32 Palmer Dabbelt
2019-05-30 5:52 ` Christoph Hellwig
2019-05-30 6:32 ` Nick Hu
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