From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE692C43461 for ; Thu, 17 Sep 2020 15:24:35 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5A2272078D for ; Thu, 17 Sep 2020 15:24:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="pDF1K0ad" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5A2272078D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=allwinnertech.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:Reply-To:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:References:MIME-Version:Subject: Message-ID:To:From:Date:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=DWF4T3hAqRBhCJy+jf1KlIGHZu9JgjcOWOePct11JJk=; b=pDF1K0adOP29jABEEWSyqcleu k+41erBB0ohmlmOKtYH6mOlYmXo8Dh5HPc21YpdSX78SD8ZXAxAknHEwe4jcqbyeOXMKbtc1TCtf4 czpuLBGJOY9DT89EPslQ6xBUzJi+donpwfDNYXth3bYUPzwVPuyjnTdPYgTMfJ5tyMdxoTn8SRubr OpHjvc++7N1P2Uh+012YZszi6XlWWHA0NlNcVp8okt1QPkn+EzHiWYJWanuSaOu0KcxpPPuUPNyiG hC9i79mWwVxOl6SF/UXLYf6ZnCLuDPzywR44J99JlXbM4CBfadlqllh6y20lpIj4PNjmV0ggE4DmC wRruuCycw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kIvlj-0004Gy-1V; Thu, 17 Sep 2020 15:24:19 +0000 Received: from smtp2207-205.mail.aliyun.com ([121.197.207.205]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kHo5m-0002O1-6Z for linux-riscv@lists.infradead.org; Mon, 14 Sep 2020 13:00:25 +0000 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07386644|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0367193-0.000737303-0.962543; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03298; MF=liush@allwinnertech.com; NM=1; PH=DW; RN=15; RT=15; SR=0; TI=W4_5948689_DEFAULT_0AB101D3_1600088414830_o7001c338u; Received: from WS-web (liush@allwinnertech.com[W4_5948689_DEFAULT_0AB101D3_1600088414830_o7001c338u]) by ay29a011140100186.et135 at Mon, 14 Sep 2020 21:00:14 +0800 Date: Mon, 14 Sep 2020 21:00:14 +0800 From: "=?UTF-8?B?5YiY6YK15Y2OQlRE?=" To: "Anup Patel" Message-ID: <3abe5394-c8ab-40ca-b01f-4e785170b409.liush@allwinnertech.com> Subject: =?UTF-8?B?5Zue5aSN77yaW1BBVENIXSBjcHVpZGxlOiBhZGQgcmlzY3YgY3B1aWRsZSBkcml2ZXI=?= X-Mailer: [Alimail-Mailagent][W4_5948689][DEFAULT][Chrome] MIME-Version: 1.0 References: <1600048323-2964-1-git-send-email-liush@allwinnertech.com>, x-aliyun-mail-creator: W4_5948689_DEFAULT_MzYTW96aWxsYS81LjAgKFdpbmRvd3MgTlQgNi4xOyBXaW42NDsgeDY0KSBBcHBsZVdlYktpdC81MzcuMzYgKEtIVE1MLCBsaWtlIEdlY2tvKSBDaHJvbWUvODUuMC40MTgzLjEwMiBTYWZhcmkvNTM3LjM2zc In-Reply-To: X-Bad-Reply: References and In-Reply-To but no 'Re:' in Subject. X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200914_090024_373665_680B31E3 X-CRM114-Status: GOOD ( 32.12 ) X-Mailman-Approved-At: Thu, 17 Sep 2020 11:24:16 -0400 X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: =?UTF-8?B?5YiY6YK15Y2OQlRE?= Cc: Damien Le Moal , Albert Ou , Daniel Lezcano , linux-pm , Anup Patel , rjw , Kefeng Wang , "linux-kernel@vger.kernel.org List" , Atish Patra , Palmer Dabbelt , Zong Li , Paul Walmsley , linux-riscv , Emil Renner Berhing Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Anup, > On Mon, Sep 14, 2020 at 7:22 AM liush wrote: > > > > This patch adds a cpuidle driver for systems based RISCV architecture. > > This patch supports state WFI. Other states will be supported in the > > future. > First of all thanks for taking up the CPUIDLE efforts for RISC-V. > The commit description can be bit simplified as follows: > "This patch adds a simple cpuidle driver for RISC-V systems using > the WFI state. Other states will be supported in the future." Thank you for your advice! Agree. > > > > Signed-off-by: liush > > --- > > arch/riscv/Kconfig | 7 +++++ > > arch/riscv/include/asm/cpuidle.h | 7 +++++ > > arch/riscv/kernel/Makefile | 1 + > > arch/riscv/kernel/cpuidle.c | 8 ++++++ > > drivers/cpuidle/Kconfig | 5 ++++ > > drivers/cpuidle/Kconfig.riscv | 11 ++++++++ > > drivers/cpuidle/Makefile | 4 +++ > > drivers/cpuidle/cpuidle-riscv.c | 55 ++++++++++++++++++++++++++++++++++++++++ > > 8 files changed, 98 insertions(+) > > create mode 100644 arch/riscv/include/asm/cpuidle.h > > create mode 100644 arch/riscv/kernel/cpuidle.c > > create mode 100644 drivers/cpuidle/Kconfig.riscv > > create mode 100644 drivers/cpuidle/cpuidle-riscv.c > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index df18372..c7ddb9d 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -86,6 +86,7 @@ config RISCV > > select SPARSE_IRQ > > select SYSCTL_EXCEPTION_TRACE > > select THREAD_INFO_IN_TASK > > + select CPU_IDLE > Place "select CPU_IDLE" in alphabetical order under > "config RISCV". Agree, I'll fix it. > > > > config ARCH_MMAP_RND_BITS_MIN > > default 18 if 64BIT > > @@ -407,6 +408,12 @@ config BUILTIN_DTB > > depends on RISCV_M_MODE > > depends on OF > > > > +menu "CPU Power Management" > > + > > +source "drivers/cpuidle/Kconfig" > > + > > +endmenu > > + > > menu "Power management options" > > > source "kernel/power/Kconfig" > > diff --git a/arch/riscv/include/asm/cpuidle.h b/arch/riscv/include/asm/cpuidle.h > > new file mode 100644 > > index 00000000..2599d2f > > --- /dev/null > > +++ b/arch/riscv/include/asm/cpuidle.h > > @@ -0,0 +1,7 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +#ifndef __RISCV_CPUIDLE_H > > +#define __RISCV_CPUIDLE_H > > + > > +extern void cpu_do_idle(void); > > + > > +#endif > > diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile > > index dc93710..396ba9c 100644 > > --- a/arch/riscv/kernel/Makefile > > +++ b/arch/riscv/kernel/Makefile > > @@ -29,6 +29,7 @@ obj-y += riscv_ksyms.o > > obj-y += stacktrace.o > > obj-y += cacheinfo.o > > obj-y += patch.o > > +obj-y += cpuidle.o > > obj-$(CONFIG_MMU) += vdso.o vdso/ > > > > obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o > > diff --git a/arch/riscv/kernel/cpuidle.c b/arch/riscv/kernel/cpuidle.c > > new file mode 100644 > > index 00000000..a3289e7 > > --- /dev/null > > +++ b/arch/riscv/kernel/cpuidle.c > > @@ -0,0 +1,8 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +#include > > + > > +void cpu_do_idle(void) > > +{ > > + __asm__ __volatile__ ("wfi"); > > + > You should directly use the wait_for_interrupt() macro defined > in asm/processor.h. Agree, I'll fix it. In addition, I want to call the fence interface mb() before call wait_for_interrupt(). > I think we don't need a separate kernel/cpuidle.c source file as > of now. Maybe in-future we can add if required. > I suggest making cpu_do_idle() as "static inline" in asm/cpuidle.h > This way you will only need asm/cpuidle.h for the current changes. Agree, I'll fix it. > > +} > > diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig > > index c0aeedd..f6be0fd 100644 > > --- a/drivers/cpuidle/Kconfig > > +++ b/drivers/cpuidle/Kconfig > > @@ -62,6 +62,11 @@ depends on PPC > > source "drivers/cpuidle/Kconfig.powerpc" > > endmenu > > > > +menu "RISCV CPU Idle Drivers" > > +depends on RISCV > > +source "drivers/cpuidle/Kconfig.riscv" > > +endmenu > > + > > config HALTPOLL_CPUIDLE > > tristate "Halt poll cpuidle driver" > > depends on X86 && KVM_GUEST > > diff --git a/drivers/cpuidle/Kconfig.riscv b/drivers/cpuidle/Kconfig.riscv > > new file mode 100644 > > index 00000000..e86d36b > > --- /dev/null > > +++ b/drivers/cpuidle/Kconfig.riscv > > @@ -0,0 +1,11 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +# > > +# RISCV CPU Idle drivers > > +# > > +config RISCV_CPUIDLE > > + bool "Generic RISCV CPU idle Driver" > > + select DT_IDLE_STATES > > + select CPU_IDLE_MULTIPLE_DRIVERS > > + help > > + Select this option to enable generic cpuidle driver for RISCV. > > + Now only support C0 State. > > diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile > > index 26bbc5e..4c83c4e 100644 > > --- a/drivers/cpuidle/Makefile > > +++ b/drivers/cpuidle/Makefile > > @@ -34,3 +34,7 @@ obj-$(CONFIG_MIPS_CPS_CPUIDLE) += cpuidle-cps.o > > # POWERPC drivers > > obj-$(CONFIG_PSERIES_CPUIDLE) += cpuidle-pseries.o > > obj-$(CONFIG_POWERNV_CPUIDLE) += cpuidle-powernv.o > > + > > +############################################################################### > > +# RISCV drivers > > +obj-$(CONFIG_RISCV_CPUIDLE) += cpuidle-riscv.o > > diff --git a/drivers/cpuidle/cpuidle-riscv.c b/drivers/cpuidle/cpuidle-riscv.c > > new file mode 100644 > > index 00000000..5dddcfa > > --- /dev/null > > +++ b/drivers/cpuidle/cpuidle-riscv.c > > @@ -0,0 +1,55 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * RISC-V CPU idle driver. > > + * > > + * Copyright (C) 2020-2022 Allwinner Ltd > > + * > > + * Based on code - driver/cpuidle/cpuidle-at91.c > > + * > > + */ > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#define MAX_IDLE_STATES 1 > > + > > +/* TODO: Implement deeper idle states */ > > +static int riscv_low_level_suspend_enter(int state) > > +{ > Shouldn't we call cpu_do_idle() here ??? I think riscv_low_level_suspend_enter is suitable for the scenario of C1, C2. In riscv_low_level_suspend_enter, SBI is called to jump to runtime firmware (opensbi or bbl)to deal with platform related tasks. > > + return 0; > > +} > > + > > +/* Actual code that puts the SoC in different idle states */ > > +static int riscv_enter_idle(struct cpuidle_device *dev, > > + struct cpuidle_driver *drv, > > + int index) > > +{ > > + return CPU_PM_CPU_IDLE_ENTER_PARAM(riscv_low_level_suspend_enter, > > + index, 0); > > +} > > + > > +static struct cpuidle_driver riscv_idle_driver = { > > + .name = "riscv_idle", > > + .owner = THIS_MODULE, > > + .states[0] = { > > + .enter = riscv_enter_idle, > > + .exit_latency = 1, > > + .target_residency = 1, > > + .name = "WFI", > > + .desc = "RISCV WFI", > > + }, > > + .state_count = MAX_IDLE_STATES, > > +}; > > + > > +static int __init riscv_cpuidle_init(void) > > +{ > > + return cpuidle_register(&riscv_idle_driver, NULL); > > +} > > + > > +device_initcall(riscv_cpuidle_init); > > -- > > 2.7.4 > > > As a separate topic, I suggest you propose the > SBI_EXT_HSM_HART_SUSPEND call for SBI spec. > The generic RISC-V cpuidle driver can detect > SBI_EXT_HSM_HART_SUSPEND availability in > riscv_cpuidle_init(). The riscv_low_level_suspend_enter() > will do SBI_EXT_HSM_HART_SUSPEND call whenever > available otherwise it can simply call cpu_do_idle(). Thank you. Your suggestion is really appreciated. In my opinion, we may propose a new SBI ID and discuss about it later. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv