From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D9E11C43219 for ; Thu, 24 Nov 2022 18:25:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4Sta6V0uQxSiqZIcjf31CZrJnusElDi4LfPoRD6ujVA=; b=qoz1LWeSaq4sdZ a69R0WILtKapKt9bsdWaGv5/+hYNZUqkK6gOHxZoZy//sjBe/FEyBJ1kNEilO+Bf65dhbhhfJGK8A I8IcjvwxG39PdEo9rqi7oR48YIa90MFuUEuNRo6NuZckmEeSxL2Hqb3tvZ+0UoCNgswNs5NYQ4HQe XDYamJsfvN6TlbZflno44oLuPTVGUgqutQ3wNitWdQWI90hMG4cngC4eyCKBQnN2YJM2jetIckI2U G0rfVfDQLal1QbH7sdE0E7XDQfumUWCzXQ0zCgX9yFoZab4Y2pmvHi6cwdkfH4Wu7TCsY2RwFrtA2 QqmOizGMRFXYVZzaPFYg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oyGuE-00AscV-JY; Thu, 24 Nov 2022 18:25:02 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oyGuC-00Asab-3y for linux-riscv@lists.infradead.org; Thu, 24 Nov 2022 18:25:01 +0000 Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oyGtz-0007HK-BN; Thu, 24 Nov 2022 19:24:47 +0100 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Guo Ren , Prabhakar Cc: Jisheng Zhang , Atish Patra , Anup Patel , Andrew Jones , Nathan Chancellor , Philipp Tomsich , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: Re: [PATCH v4 3/7] riscv: errata: Add Andes alternative ports Date: Thu, 24 Nov 2022 19:24:46 +0100 Message-ID: <4542837.QJadu78ljV@diego> In-Reply-To: <20221124172207.153718-4-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221124172207.153718-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221124172207.153718-4-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221124_102500_185608_1D90577A X-CRM114-Status: GOOD ( 20.39 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Am Donnerstag, 24. November 2022, 18:22:03 CET schrieb Prabhakar: > From: Lad Prabhakar > > Add required ports of the Alternative scheme for Andes CPU cores. > > Signed-off-by: Lad Prabhakar > --- > RFC v3 -> v4 > * New patch > --- > diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile > index a1055965fbee..81828e80f6dc 100644 > --- a/arch/riscv/errata/Makefile > +++ b/arch/riscv/errata/Makefile > @@ -1,2 +1,3 @@ > obj-$(CONFIG_ERRATA_SIFIVE) += sifive/ > obj-$(CONFIG_ERRATA_THEAD) += thead/ > +obj-$(CONFIG_ERRATA_ANDES) += andes/ alphabetical sorting please > diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c > new file mode 100644 > index 000000000000..ec3e052ca8c7 > --- /dev/null > +++ b/arch/riscv/errata/andes/errata.c > @@ -0,0 +1,68 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Erratas to be applied for Andes CPU cores > + * > + * Copyright (C) 2022 Renesas Electronics Corporation. > + * > + * Author: Lad Prabhakar > + */ > + > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > + > +static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigned long impid) > +{ > + if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO)) > + return false; > + > + if (arch_id != 0x8000000000008a45 || impid != 0x500) > + return false; > + > + riscv_cbom_block_size = 1; as this is mainly to make the core cbo code happy, maybe add a comment above that line to explain. > + riscv_noncoherent_supported(); > + > + return true; > +} > + > diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h > index 6511dd73e812..d8012af30cbd 100644 > --- a/arch/riscv/include/asm/alternative.h > +++ b/arch/riscv/include/asm/alternative.h > @@ -46,6 +46,9 @@ void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, > void thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, > unsigned long archid, unsigned long impid, > unsigned int stage); > +void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, > + unsigned long archid, unsigned long impid, > + unsigned int stage); again alphabetical please (i.e. above sifive) > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h > index 4180312d2a70..2ba7e6e74540 100644 > --- a/arch/riscv/include/asm/errata_list.h > +++ b/arch/riscv/include/asm/errata_list.h > @@ -9,6 +9,11 @@ > #include > #include > > +#ifdef CONFIG_ERRATA_ANDES > +#define ERRATA_ANDESTECH_NO_IOCP 0 > +#define ERRATA_ANDESTECH_NUMBER 1 > +#endif > + > #ifdef CONFIG_ERRATA_SIFIVE > #define ERRATA_SIFIVE_CIP_453 0 > #define ERRATA_SIFIVE_CIP_1200 1 > diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c > index a7d26a00beea..4ded3e9aa3bc 100644 > --- a/arch/riscv/kernel/alternative.c > +++ b/arch/riscv/kernel/alternative.c > @@ -47,6 +47,11 @@ static void __init_or_module riscv_fill_cpu_mfr_info(struct cpu_manufacturer_inf > case THEAD_VENDOR_ID: > cpu_mfr_info->patch_func = thead_errata_patch_func; > break; > +#endif > +#ifdef CONFIG_ERRATA_ANDES > + case ANDESTECH_VENDOR_ID: > + cpu_mfr_info->patch_func = andes_errata_patch_func; > + break; and again alphabetical please Thanks Heiko _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv