From: "Arnd Bergmann" <arnd@arndb.de>
To: "Palmer Dabbelt" <palmer@dabbelt.com>,
"Anup Patel" <apatel@ventanamicro.com>
Cc: "Paul Walmsley" <paul.walmsley@sifive.com>,
"Atish Patra" <atishp@atishpatra.org>,
"Heiko Stübner" <heiko@sntech.de>,
anup@brainfault.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, mchitale@ventanamicro.com
Subject: Re: [PATCH v2 1/4] RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt
Date: Fri, 23 Sep 2022 12:35:50 +0200 [thread overview]
Message-ID: <45de6e04-b19b-4ffe-878e-6ba8123f2aef@www.fastmail.com> (raw)
In-Reply-To: <mhng-37586d5e-5576-448a-8d9c-4d277c252365@palmer-ri-x1c9>
On Thu, Sep 22, 2022, at 6:35 PM, Palmer Dabbelt wrote:
> On Thu, 15 Sep 2022 19:24:55 PDT (-0700), apatel@ventanamicro.com wrote:
>>
>> On Tue, Aug 30, 2022 at 10:17 AM Anup Patel <apatel@ventanamicro.com> wrote:
>>>
>>> Currently, all flavors of ioremap_xyz() function maps to the generic
>>> ioremap() which means any ioremap_xyz() call will always map the
>>> target memory as IO using _PAGE_IOREMAP page attributes. This breaks
>>> ioremap_cache() and ioremap_wc() on systems with Svpbmt because memory
>>> remapped using ioremap_cache() and ioremap_wc() will use _PAGE_IOREMAP
>>> page attributes.
>>>
>>> To address above (just like other architectures), we implement RISC-V
>>> specific ioremap_cache() and ioremap_wc() which maps memory using page
>>> attributes as defined by the Svpbmt specification.
>>>
>>> Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support")
>>> Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
>>> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
>>> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
>>
>> This is a crucial RC fix. Can you please take this ?
>
> Sorry I missed this, I thought it was just part of the rest of this
> patch set. That said, I'm not actually sure this is a critical fix:
> sure it's a performance problem, and if some driver is expecting
> ioremap_cache() to go fast then possibly a pretty big one, but the only
> Svpmbt hardware that exists is the D1 and that was just supported this
> release so it's not a regression. Maybe that's a bit pedantic, but all
> this travel has kind of made things a mess and I'm trying to make sure
> nothing goes off the rails.
I think generally speaking any use of ioremap_cache() in a driver
is a mistake. The few users that exist are usually from historic
x86 specific code and are hard to kill off.
Arnd
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next prev parent reply other threads:[~2022-09-23 10:36 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-30 4:46 [PATCH v2 0/4] Add PMEM support for RISC-V Anup Patel
2022-08-30 4:46 ` [PATCH v2 1/4] RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt Anup Patel
2022-09-01 15:25 ` Heiko Stübner
2022-09-01 16:07 ` Conor.Dooley
2022-09-09 8:10 ` Anup Patel
2022-09-16 2:24 ` Anup Patel
2022-09-22 16:35 ` Palmer Dabbelt
2022-09-23 10:35 ` Arnd Bergmann [this message]
2022-09-23 10:45 ` Palmer Dabbelt
2022-09-28 12:14 ` Christoph Hellwig
2022-10-07 3:50 ` Palmer Dabbelt
2022-10-07 5:34 ` Anup Patel
2022-08-30 4:46 ` [PATCH v2 2/4] RISC-V: Move riscv_init_cbom_blocksize() to cacheflush.c Anup Patel
2022-09-01 15:29 ` Heiko Stübner
2022-09-01 15:49 ` Conor.Dooley
2022-08-30 4:46 ` [PATCH v2 3/4] RISC-V: Implement arch specific PMEM APIs Anup Patel
2022-09-01 15:38 ` Heiko Stübner
2022-09-03 16:03 ` Anup Patel
2022-08-30 4:46 ` [PATCH v2 4/4] RISC-V: Enable PMEM drivers Anup Patel
2022-09-01 16:11 ` Conor.Dooley
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