From: Greentime Hu <greentime.hu@sifive.com>
To: greentime.hu@sifive.com, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu,
palmer@dabbelt.com, paul.walmsley@sifive.com
Subject: [PATCH 2/2] riscv: Simplify the checking for SR_PP
Date: Mon, 13 Jul 2020 16:32:16 +0800 [thread overview]
Message-ID: <4bac52941700cd7b714a41606df7b53f4cf24824.1594629047.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <742f0a82a9d4ab62d8616784db5a88a95d8b5389.1594629047.git.greentime.hu@sifive.com>
This patch simplifies the checking for SR_MPP and SR_SPP. It uses SR_PP in the
code flow for both m-mode and s-mode then we can remove the ifdef here.
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
---
arch/riscv/kernel/entry.S | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 000984695cd6..597beae0d238 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -210,13 +210,8 @@ ret_from_syscall_rejected:
ret_from_exception:
REG_L s0, PT_STATUS(sp)
csrc CSR_STATUS, SR_IE
-#ifdef CONFIG_RISCV_M_MODE
- /* the MPP value is too large to be used as an immediate arg for addi */
- li t0, SR_MPP
+ li t0, SR_PP
and s0, s0, t0
-#else
- andi s0, s0, SR_SPP
-#endif
bnez s0, resume_kernel
resume_userspace:
--
2.27.0
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next prev parent reply other threads:[~2020-07-13 8:32 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-13 8:32 [PATCH 1/2] riscv: Fix building error in entry.S when CONFIG_RISCV_M_MODE is enabled Greentime Hu
2020-07-13 8:32 ` Greentime Hu [this message]
2020-07-22 2:59 ` [PATCH 2/2] riscv: Simplify the checking for SR_PP Palmer Dabbelt
2020-07-13 20:11 ` [PATCH 1/2] riscv: Fix building error in entry.S when CONFIG_RISCV_M_MODE is enabled Palmer Dabbelt
2020-07-22 2:58 ` Palmer Dabbelt
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