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From: Atish Patra <Atish.Patra@wdc.com>
To: "hch@lst.de" <hch@lst.de>,
	"troy.benjegerdes@sifive.com" <troy.benjegerdes@sifive.com>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"palmer@sifive.com" <palmer@sifive.com>,
	Damien Le Moal <Damien.LeMoal@wdc.com>,
	"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>
Subject: Re: [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode
Date: Wed, 21 Aug 2019 17:31:00 +0000	[thread overview]
Message-ID: <4f1677e24a5fcdfd2fda714cdd66f4dbe7817284.camel@wdc.com> (raw)
In-Reply-To: <3BF39A0F-558D-40E0-880D-27829486F9F0@sifive.com>

On Tue, 2019-08-20 at 21:14 -0700, Troy Benjegerdes wrote:
> > On Aug 13, 2019, at 8:47 AM, Christoph Hellwig <hch@lst.de> wrote:
> > 
> > No point in bloating the kernel image with a bootloader header if
> > we run bare metal.
> 
> I would say the same for S-mode. EFI booting should be an option, not
> a requirement. 

EFI booting is never a requirement on any board. When EFI stub will be
added for kernel, it will be enabled with CONFIG_EFI_STUB only. 

The current additional header is only 64 bytes and also required for
booti in U-boot. So it shouldn't disabled for S-mode.
 
Disabling it for M-Mode Linux is okay because of memory constraint and
M-Mode linux won't use U-boot anyways.

> I have M-mode U-boot working with bootelf to start BBL,
> and at some point, I’m hoping we can have a M-mode linux kernel be
> the SBI provider for S-mode kernels, 

Why do you want bloat a M-Mode software with Linux just for SBI
implementation?

Using Linux as a last stage boot loader i.e. LinuxBoot may make sense
though.

> which seem most logical to me
> to start using the vmlinux elf binaries using something like kexec()
> 
> > Signed-off-by: Christoph Hellwig <hch@lst.de>
> > ---
> > arch/riscv/kernel/head.S | 2 ++
> > 1 file changed, 2 insertions(+)
> > 
> > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> > index 670e5cacb24e..09fcf3d000c0 100644
> > --- a/arch/riscv/kernel/head.S
> > +++ b/arch/riscv/kernel/head.S
> > @@ -16,6 +16,7 @@
> > 
> > __INIT
> > ENTRY(_start)
> > +#ifndef CONFIG_M_MODE
> > 	/*
> > 	 * Image header expected by Linux boot-loaders. The image
> > header data
> > 	 * structure is described in asm/image.h.
> > @@ -47,6 +48,7 @@ ENTRY(_start)
> > 
> > .global _start_kernel
> > _start_kernel:
> > +#endif /* CONFIG_M_MODE */
> > 	/* Mask all interrupts */
> > 	csrw CSR_XIE, zero
> > 	csrw CSR_XIP, zero
> > -- 
> > 2.20.1
> > 
> > 
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

-- 
Regards,
Atish
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  parent reply	other threads:[~2019-08-21 17:31 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-13 15:47 RISC-V nommu support v3 Christoph Hellwig
2019-08-13 15:47 ` [PATCH 01/15] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig
2019-08-13 17:44   ` Paul Walmsley
2019-08-14  9:06     ` Marc Zyngier
2019-08-13 15:47 ` [PATCH 02/15] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm Christoph Hellwig
2019-08-13 16:36   ` Paul Walmsley
2019-08-13 16:42     ` Christoph Hellwig
2019-08-13 16:51       ` Paul Walmsley
2019-08-13 19:44   ` Paul Walmsley
2019-08-13 15:47 ` [PATCH 03/15] riscv: refactor the IPI code Christoph Hellwig
2019-08-14  4:41   ` Paul Walmsley
2019-08-19 10:18     ` Christoph Hellwig
2019-09-01  8:03     ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 04/15] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-08-13 15:47 ` [PATCH 05/15] riscv: improve the default power off implementation Christoph Hellwig
2019-08-13 15:47 ` [PATCH 06/15] riscv: provide a flat entry loader Christoph Hellwig
2019-08-13 15:47 ` [PATCH 07/15] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-08-13 15:47 ` [PATCH 08/15] riscv: provide native clint access for M-mode Christoph Hellwig
2019-08-13 16:29   ` Mark Rutland
2019-08-19 10:16     ` Christoph Hellwig
2019-08-27 23:37       ` Palmer Dabbelt
2019-08-28  6:11         ` Christoph Hellwig
2019-09-03 18:48           ` Palmer Dabbelt
2019-09-04  2:05             ` Alan Kao
2019-08-21  0:24   ` Atish Patra
2019-08-21  0:42     ` hch
2019-08-13 15:47 ` [PATCH 09/15] riscv: implement remote sfence.i natively " Christoph Hellwig
2019-08-20 21:04   ` Atish Patra
2019-08-13 15:47 ` [PATCH 10/15] riscv: poison SBI calls " Christoph Hellwig
2019-08-20 21:05   ` Atish Patra
2019-08-13 15:47 ` [PATCH 11/15] riscv: don't allow selecting SBI-based drivers " Christoph Hellwig
2019-08-13 15:47 ` [PATCH 12/15] riscv: use the correct interrupt levels " Christoph Hellwig
2019-08-13 15:47 ` [PATCH 13/15] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-08-14  1:00   ` Alan Kao
2019-08-14  1:07     ` Alan Kao
2019-08-14  4:35     ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 14/15] riscv: add nommu support Christoph Hellwig
2019-08-13 15:47 ` [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-08-20 21:07   ` Atish Patra
2019-08-21  4:14   ` Troy Benjegerdes
2019-08-21  7:12     ` Christoph Hellwig
2019-08-21 17:31     ` Atish Patra [this message]
2019-08-21 17:54       ` Troy Benjegerdes
2019-08-21 23:02         ` Anup Patel
2019-08-21 23:32           ` Troy Benjegerdes
2019-10-17 17:37 RISC-V nommu support v5 Christoph Hellwig
2019-10-17 17:37 ` [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-10-18  3:06   ` Anup Patel

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