From: Zong Li <zong.li@sifive.com>
To: palmer@dabbelt.com, paul.walmsley@sifive.com,
aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: Zong Li <zong.li@sifive.com>
Subject: [PATCH v2 7/9] riscv: add macro to get instruction length
Date: Mon, 9 Mar 2020 16:22:27 +0800 [thread overview]
Message-ID: <59d5cd2e5325893f3cff9420e7e94d5c0f503da1.1583741997.git.zong.li@sifive.com> (raw)
In-Reply-To: <cover.1583741997.git.zong.li@sifive.com>
Extract the calculation of instruction length for common use.
Signed-off-by: Zong Li <zong.li@sifive.com>
---
arch/riscv/include/asm/bug.h | 8 ++++++++
arch/riscv/kernel/traps.c | 3 ++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/bug.h b/arch/riscv/include/asm/bug.h
index 75604fec1b1b..d6f1ec08d97b 100644
--- a/arch/riscv/include/asm/bug.h
+++ b/arch/riscv/include/asm/bug.h
@@ -19,6 +19,14 @@
#define __BUG_INSN_32 _UL(0x00100073) /* ebreak */
#define __BUG_INSN_16 _UL(0x9002) /* c.ebreak */
+#define GET_INSN_LENGTH(insn) \
+({ \
+ unsigned long __len; \
+ __len = ((insn & __INSN_LENGTH_MASK) == __INSN_LENGTH_32) ? \
+ 4UL : 2UL; \
+ __len; \
+})
+
typedef u32 bug_insn_t;
#ifdef CONFIG_GENERIC_BUG_RELATIVE_POINTERS
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index ffb3d94bf0cc..a4d136355f78 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -118,7 +118,8 @@ static inline unsigned long get_break_insn_length(unsigned long pc)
if (probe_kernel_address((bug_insn_t *)pc, insn))
return 0;
- return (((insn & __INSN_LENGTH_MASK) == __INSN_LENGTH_32) ? 4UL : 2UL);
+
+ return GET_INSN_LENGTH(insn);
}
asmlinkage __visible void do_trap_break(struct pt_regs *regs)
--
2.25.1
next prev parent reply other threads:[~2020-03-09 8:23 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-09 8:22 [PATCH v2 0/9] Support strict kernel memory permissions for security Zong Li
2020-03-09 8:22 ` [PATCH v2 1/9] riscv: add ARCH_HAS_SET_MEMORY support Zong Li
2020-03-09 12:50 ` kbuild test robot
2020-03-09 8:22 ` [PATCH v2 2/9] riscv: add ARCH_HAS_SET_DIRECT_MAP support Zong Li
2020-03-09 8:22 ` [PATCH v2 3/9] riscv: add ARCH_SUPPORTS_DEBUG_PAGEALLOC support Zong Li
2020-03-09 8:22 ` [PATCH v2 4/9] riscv: move exception table immediately after RO_DATA Zong Li
2020-03-09 8:22 ` [PATCH v2 5/9] riscv: add alignment for text, rodata and data sections Zong Li
2020-03-09 8:22 ` [PATCH v2 6/9] riscv: add STRICT_KERNEL_RWX support Zong Li
2020-03-09 13:13 ` kbuild test robot
2020-03-09 8:22 ` Zong Li [this message]
2020-03-09 8:22 ` [PATCH v2 8/9] riscv: introduce interfaces to patch kernel code Zong Li
2020-03-09 12:49 ` kbuild test robot
2020-03-09 13:12 ` kbuild test robot
2020-03-09 8:22 ` [PATCH v2 9/9] riscv: patch code by fixmap mapping Zong Li
2020-03-09 8:33 ` [PATCH v2 0/9] Support strict kernel memory permissions for security Zong Li
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=59d5cd2e5325893f3cff9420e7e94d5c0f503da1.1583741997.git.zong.li@sifive.com \
--to=zong.li@sifive.com \
--cc=aou@eecs.berkeley.edu \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).