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Mon, 12 Aug 2019 12:49:07 -0700 (PDT) Subject: Re: [PATCH] riscv: kbuild: drop CONFIG_RISCV_ISA_C To: Christoph Hellwig , Charles Papon References: <20190812150348.GH26897@infradead.org> From: Darius Rad Message-ID: <5a931461-c6a8-6d2d-4f73-103a10b26f0e@bluespec.com> Date: Mon, 12 Aug 2019 15:49:06 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190812150348.GH26897@infradead.org> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190812_124909_779260_C42CA59E X-CRM114-Status: GOOD ( 11.41 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , linux-riscv , Bin Meng , linux-kernel , Paul Walmsley Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On 8/12/19 11:03 AM, Christoph Hellwig wrote: > On Thu, Aug 08, 2019 at 02:18:53PM +0200, Charles Papon wrote: >> Please do not drop it. >> >> Compressed instruction extension has some specific overhead in small >> RISC-V FPGA softcore, especialy in the ones which can't implement the >> register file read in a asynchronous manner because of the FPGA >> technology. >> What are reasons to enforce RVC ? > > Because it it the unix platform baseline as stated in the patch. > The same argument could be made for an FPU or MMU, yet there are options to disable those. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv