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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id v6sm913853oie.4.2019.09.13.07.36.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Sep 2019 07:36:27 -0700 (PDT) Message-ID: <5d7ba96b.1c69fb81.edf8e.655e@mx.google.com> Date: Fri, 13 Sep 2019 15:36:26 +0100 From: Rob Herring To: Pragnesh Patel Subject: Re: [PATCH] spi: dt-bindings: Convert spi-sifive binding to json-schema References: <1568098996-4180-1-git-send-email-pragnesh.patel@sifive.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1568098996-4180-1-git-send-email-pragnesh.patel@sifive.com> X-Mutt-References: <1568098996-4180-1-git-send-email-pragnesh.patel@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190913_073629_667110_B0E33D94 X-CRM114-Status: GOOD ( 16.64 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, palmer@sifive.com, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, Mark Brown , paul.walmsley@sifive.com, linux-riscv@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Sep 10, 2019 at 12:32:51PM +0530, Pragnesh Patel wrote: > Convert the spi-sifive binding to DT schema format. > > Signed-off-by: Pragnesh Patel > --- > .../devicetree/bindings/spi/spi-sifive.txt | 37 ---------- > .../devicetree/bindings/spi/spi-sifive.yaml | 86 ++++++++++++++++++++++ > 2 files changed, 86 insertions(+), 37 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/spi/spi-sifive.txt > create mode 100644 Documentation/devicetree/bindings/spi/spi-sifive.yaml > diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml b/Documentation/devicetree/bindings/spi/spi-sifive.yaml > new file mode 100644 > index 0000000..368f5d5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/spi/spi-sifive.yaml > @@ -0,0 +1,86 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/spi/spi-sifive.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SiFive SPI controller > + > +maintainers: > + - Pragnesh Patel > + - Paul Walmsley > + - Palmer Dabbelt > + > +allOf: > + - $ref: "spi-controller.yaml#" > + > +properties: > + compatible: > + items: > + - const: sifive,fu540-c000-spi > + - const: sifive,spi0 > + > + description: > + Should be "sifive,-spi" and "sifive,spi". > + Supported compatible strings are - > + "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated > + onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive > + SPI v0 IP block with no chip integration tweaks. > + Please refer to sifive-blocks-ip-versioning.txt for details > + > + SPI RTL that corresponds to the IP block version numbers can be found here - > + https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi > + > + reg: > + maxItems: 1 > + > + description: > + Physical base address and size of SPI registers map > + A second (optional) range can indicate memory mapped flash > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + description: > + Must reference the frequency given to the controller > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 These 2 are covered by spi-controller.yaml, so you can drop them. > + > + sifive,fifo-depth: > + description: > + Depth of hardware queues; defaults to 8 default: 8 What are valid values? > + $ref: "/schemas/types.yaml#/definitions/uint32" Will need to be under 'allOf' with the above constraints. > + > + sifive,max-bits-per-word: > + description: > + Maximum bits per word; defaults to 8 > + $ref: "/schemas/types.yaml#/definitions/uint32" Same comments here. > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + > +examples: > + - | > + spi: spi@10040000 { > + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; > + reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>; > + interrupt-parent = <&plic>; > + interrupts = <51>; > + clocks = <&tlclk>; > + #address-cells = <1>; > + #size-cells = <0>; > + sifive,fifo-depth = <8>; > + sifive,max-bits-per-word = <8>; > + }; > + > +... > -- > 2.7.4 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv