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From: <Conor.Dooley@microchip.com>
To: <xianting.tian@linux.alibaba.com>, <paul.walmsley@sifive.com>,
	<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
	<anup@brainfault.org>, <heiko@sntech.de>, <guoren@kernel.org>,
	<mick@ics.forth.gr>, <alexandre.ghiti@canonical.com>,
	<bhe@redhat.com>, <vgoyal@redhat.com>, <dyoung@redhat.com>,
	<corbet@lwn.net>
Cc: <kexec@lists.infradead.org>, <linux-doc@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<crash-utility@redhat.com>, <huanyi.xj@alibaba-inc.com>,
	<heinrich.schuchardt@canonical.com>, <k-hagio-ab@nec.com>,
	<hschauhan@nulltrace.org>
Subject: Re: [PATCH V4 0/5] RISC-V fixups to work with crash tool
Date: Tue, 26 Jul 2022 09:52:00 +0000	[thread overview]
Message-ID: <651b552d-8954-e58c-e994-4a9782f1112a@microchip.com> (raw)
In-Reply-To: <20220726093729.1231867-1-xianting.tian@linux.alibaba.com>

On 26/07/2022 10:37, Xianting Tian wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe

Ah I see you've already sent a v4.

> 
> Changes v1 -> v2:
>   1, remove the patch "Add a fast call path of crash_kexec()" from this series
>   of patches, as it already applied to riscv git.
>   https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/commit/?h=for-next&id=3f1901110a89b0e2e13adb2ac8d1a7102879ea98
>   2, add 'Reviewed-by' based on the comments of v1.
> Changes v2 -> v3:
>   use "riscv" instead of "riscv64" in patch 5 subject line.
> Changes v3 -> v4:
>   use "riscv" instead of "riscv64" in the summary of patch 5 subject line.

There's no need to respin a series for the sake 3 characters in the cover
letter (so sorry if you misunderstood me!)...

> 
> Xianting Tian (5):
>    RISC-V: use __smp_processor_id() instead of smp_processor_id()
>    RISC-V: Add arch_crash_save_vmcoreinfo support
>    riscv: Add modules to virtual kernel memory layout dump
>    RISC-V: Fixup getting correct current pc
>    riscv: crash_core: Export kernel vm layout, phys_ram_base

...but it would've been good to align these to either "riscv:" or
"RISC-V:" & not mix the two in a series. Don't do this right away,
it is okay to wait for more significant changes before sending out
a new version as this sort of thing could easily be changed when
being applied.

Thanks,
Conor.


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  parent reply	other threads:[~2022-07-26  9:52 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-26  9:37 [PATCH V4 0/5] RISC-V fixups to work with crash tool Xianting Tian
2022-07-26  9:37 ` [PATCH V4 1/5] RISC-V: use __smp_processor_id() instead of smp_processor_id() Xianting Tian
2022-07-26  9:37 ` [PATCH V4 2/5] RISC-V: Add arch_crash_save_vmcoreinfo support Xianting Tian
2022-07-26  9:37 ` [PATCH V4 3/5] riscv: Add modules to virtual kernel memory layout dump Xianting Tian
2022-07-26  9:37 ` [PATCH V4 4/5] RISC-V: Fixup getting correct current pc Xianting Tian
2022-07-26  9:37 ` [PATCH V4 5/5] riscv: crash_core: Export kernel vm layout, phys_ram_base Xianting Tian
2022-07-26  9:52 ` Conor.Dooley [this message]
2022-07-26 13:58   ` [PATCH V4 0/5] RISC-V fixups to work with crash tool Xianting Tian

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