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([2001:b07:6468:f312:29d3:6123:6d5f:2c04]) by smtp.gmail.com with ESMTPSA id y6sm56247471wrp.12.2019.07.30.02.00.08 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Tue, 30 Jul 2019 02:00:08 -0700 (PDT) Subject: Re: [RFC PATCH 11/16] RISC-V: KVM: Implement stage2 page table programming To: Anup Patel , Palmer Dabbelt , Paul Walmsley , Radim K References: <20190729115544.17895-1-anup.patel@wdc.com> <20190729115544.17895-12-anup.patel@wdc.com> From: Paolo Bonzini Message-ID: <6ebde80e-e8a9-6b7b-52ea-656b9a9e5e5b@redhat.com> Date: Tue, 30 Jul 2019 11:00:07 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190729115544.17895-12-anup.patel@wdc.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190730_020015_969625_660B63EA X-CRM114-Status: UNSURE ( 9.39 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On 29/07/19 13:57, Anup Patel wrote: > This patch implements all required functions for programming > the stage2 page table for each Guest/VM. > > At high-level, the flow of stage2 related functions is similar > from KVM ARM/ARM64 implementation but the stage2 page table > format is quite different for KVM RISC-V. FWIW I very much prefer KVM x86's recursive implementation of the MMU to the hardcoding of pgd/pmd/pte. I am not asking you to rewrite it, but I'll mention it because I noticed that you do not support 48-bit guest physical addresses. Paolo _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv