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DIR:OUT; SFP:1102; SCL:1; SRVR:LO2P265MB1295; H:LO2P265MB0847.GBRP265.PROD.OUTLOOK.COM; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: garyguo.net does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: gRkqUT0ojW2+YIiyvG6RnQ6c3o/lfOABCyb44F0ii5Iix6SwYRPbr1B+oQ5ArF4pFodmWpKmmTPa8KQf7GLr+qgv8oGJ1lHkRHt9GbgZpmjLfo8pnyOJ5qJZxpVz8h2pXwu9a5qrC9i0z5tYLMR+6hnbpOlJiM1IoOhHOETgDQx0nloj5p7r2uLepMev9f8zj886zuvBvKL9bqyvrKVglZ5uJwDUHvXEWGWNtVo1F0sz9+2DIyFEz25ptoHMwngIiH4yCmCMBL7JxBcWt/wxJRD42wYAF1r43z6r4oo8AcPS0zt42LdpngIToQLC2rFDlHqQ7jbYZOsohqPHMUMQpQZWqZcm0NpdxVESgFBW2935agciuoU/5sNwdSau7/BznUt8CYzmSH3WcKLPv/2ss3XDJFOsFRn55byGPmDNI8A= Content-ID: MIME-Version: 1.0 X-OriginatorOrg: garyguo.net X-MS-Exchange-CrossTenant-Network-Message-Id: bae4e099-0b80-49ec-8e6f-08d6b2ba0db6 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Mar 2019 13:42:28.4833 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: bbc898ad-b10f-4e10-8552-d9377b823d45 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: LO2P265MB1295 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190327_064236_704499_52DB9865 X-CRM114-Status: GOOD ( 18.89 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , Anup Patel , "linux-kernel@vger.kernel.org" , Mike Rapoport , Christoph Hellwig , Atish Patra , Albert Ou , Paul Walmsley , "linux-riscv@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org I would also like to mention that your code assumes 64-bit atomics support which we don't have on 32-bit systems. Using 32-bit to track ASID generations isn't sufficient and will cause overflows. That's why I have asid_generation_overflow to handle the case (this is super error-prone as well). Best, Gary On 27/03/2019 11:42, Anup Patel wrote: > On Wed, Mar 27, 2019 at 4:57 PM Gary Guo wrote: >> >> Hi Anup, >> >> This won't work in an actual hardware with ASID support. There're more > > Can you elaborate why? > > This implementation is based on Linux ARM64 ASID allocator which is > tested for large number of CPUs on real HW. > >> interactions with TLB flushes that need to be considered. You won't see > > Yap, already considered. Please point me to unhandled case. > >> this on both QEMU and SiFive board, as QEMU does not have ASID, so it >> pretends that ASID is supported by just flushing its TLB everytime you > > Nope, it does not. It detects whether ASID is supported or not. If supported > it will also figure-out number of ASID bits supported by HW. > > SiFive board does not have ASID bits so this implementation successfully > detects that number of ASID bits are 0 and fallbacks to original way of > local TLB flushes. > >> change sptbr. I suspect the performance gain you see is just due to >> saved TLB flush as TLB flush is super expensive in QEMU (all translation >> block jumps need to be cleared). > > Yes, performance gain is due to saved TLB flushes. > > On HW which supports ASID bits, we will see more performance > improvements. > >> >> I have my version here https://github.com/nbdd0121/linux/tree/asid. I >> haven't done code cleanups yet, but this version has correctness of its >> ASID code tested on our TLB simulator tool (which unfortunately I can't >> share right now as it involves with unpublished works). > > Except few minor differences. You version of ASID allocator is same as > mine. In fact there are lot of similar code framgements in your version > compared to Linux ARM64 as well. I am sure this patch will work for you. > >> >> In fact my submit my previous patch series exactly as the basis of this >> patch. > > This patch is based your patch series so I suggest you take this patch > and try it on your simulator. > > Suggestions and improvements to this patch are welcomed. > > I would be happy if you can assist me to try on your HW. > > Regards, > Anup > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv