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X-IronPort-AV: E=Sophos;i="5.56,327,1539619200"; d="scan'208";a="96112436" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 08 Dec 2018 07:31:25 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP; 07 Dec 2018 15:14:09 -0800 Received: from gj0bt32.ad.shared (HELO [10.86.57.164]) ([10.86.57.164]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Dec 2018 15:31:24 -0800 Subject: Re: [PATCH 4/4] RISC-V: Fix non-smp kernel boot on SMP systems To: Palmer Dabbelt References: From: Atish Patra Message-ID: <74dcf9b4-2343-0f56-1b56-80cc064728fb@wdc.com> Date: Fri, 7 Dec 2018 15:31:23 -0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:60.0) Gecko/20100101 Thunderbird/60.3.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181207_153137_964153_73F19036 X-CRM114-Status: GOOD ( 17.35 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , Damien Le Moal , "aou@eecs.berkeley.edu" , "dmitriy@oss-tech.org" , "anup@brainfault.org" , "daniel.lezcano@linaro.org" , "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , "linux-riscv@lists.infradead.org" , "tglx@linutronix.de" Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On 12/7/18 9:00 AM, Palmer Dabbelt wrote: > On Mon, 03 Dec 2018 12:57:31 PST (-0800), atish.patra@wdc.com wrote: >> Currently, clocksource registration happens for an invalid cpu >> for non-smp kernels. This lead to kernel panic as cpu hotplug >> registration will fail for those cpus. >> >> Do not proceed if hartid is invalid. Take this opprtunity to >> print appropriate error strings for different failure cases. >> >> Signed-off-by: Atish Patra >> --- >> drivers/clocksource/riscv_timer.c | 13 ++++++++++--- >> 1 file changed, 10 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c >> index 39de6e49..4af4af47 100644 >> --- a/drivers/clocksource/riscv_timer.c >> +++ b/drivers/clocksource/riscv_timer.c >> @@ -108,6 +108,8 @@ static int __init riscv_timer_init_dt(struct device_node *n) >> int cpuid, hartid, error; >> >> hartid = riscv_of_processor_hartid(n); >> + if (hartid < 0) >> + return hartid; > > This seems like it's just hiding a bug somewhere else. We should at least put > out a WARN here, as I'm not sure the error will propagate anywhere useful. > ok. I will add a warning here. That's what we are doing in plic as well. Regards, Atish >> cpuid = riscv_hartid_to_cpuid(hartid); >> >> if (cpuid != smp_processor_id()) >> @@ -115,14 +117,19 @@ static int __init riscv_timer_init_dt(struct device_node *n) >> >> /* This should be called only for boot cpu */ >> riscv_timebase = riscv_timebase_frequency(n); >> - clocksource_register_hz(&riscv_clocksource, riscv_timebase); >> + error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); >> >> + if (error) { >> + pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", >> + error, cpuid); >> + return error; >> + } >> error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING, >> "clockevents/riscv/timer:starting", >> riscv_timer_starting_cpu, riscv_timer_dying_cpu); >> if (error) >> - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", >> - error, cpuid); >> + pr_err("cpu hp setup state failed for RISCV timer [%d]\n", >> + error); >> return error; >> } > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv