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From: Atish Patra <Atish.Patra@wdc.com>
To: "hch@lst.de" <hch@lst.de>,
	"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
	"palmer@sifive.com" <palmer@sifive.com>
Cc: "linux-mm@kvack.org" <linux-mm@kvack.org>,
	Damien Le Moal <Damien.LeMoal@wdc.com>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 16/17] riscv: clear the instruction cache and all registers when booting
Date: Mon, 1 Jul 2019 21:26:18 +0000
Message-ID: <78919862d11f6d56446f8fffd8a1a8c601ea5c32.camel@wdc.com> (raw)
In-Reply-To: <20190624054311.30256-17-hch@lst.de>

On Mon, 2019-06-24 at 07:43 +0200, Christoph Hellwig wrote:
> When we get booted we want a clear slate without any leaks from
> previous
> supervisors or the firmware.  Flush the instruction cache and then
> clear
> all registers to known good values.  This is really important for the
> upcoming nommu support that runs on M-mode, but can't really harm
> when
> running in S-mode either.

That means it should be done for S-mode as well. Right ?
I see the reset code is enabled only for M-mode only.

>   Vaguely based on the concepts from opensbi.
> 
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
>  arch/riscv/kernel/head.S | 85
> ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 85 insertions(+)
> 
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index a4c170e41a34..74feb17737b4 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -11,6 +11,7 @@
>  #include <asm/thread_info.h>
>  #include <asm/page.h>
>  #include <asm/csr.h>
> +#include <asm/hwcap.h>
>  
>  __INIT
>  ENTRY(_start)
> @@ -19,6 +20,12 @@ ENTRY(_start)
>  	csrw CSR_XIP, zero
>  
>  #ifdef CONFIG_M_MODE
> +	/* flush the instruction cache */
> +	fence.i
> +
> +	/* Reset all registers except ra, a0, a1 */
> +	call reset_regs
> +
>  	/*
>  	 * The hartid in a0 is expected later on, and we have no
> firmware
>  	 * to hand it to us.
> @@ -168,6 +175,84 @@ relocate:
>  	j .Lsecondary_park
>  END(_start)
>  
> +#ifdef CONFIG_M_MODE
> +ENTRY(reset_regs)
> +	li	sp, 0
> +	li	gp, 0
> +	li	tp, 0
> +	li	t0, 0
> +	li	t1, 0
> +	li	t2, 0
> +	li	s0, 0
> +	li	s1, 0
> +	li	a2, 0
> +	li	a3, 0
> +	li	a4, 0
> +	li	a5, 0
> +	li	a6, 0
> +	li	a7, 0
> +	li	s2, 0
> +	li	s3, 0
> +	li	s4, 0
> +	li	s5, 0
> +	li	s6, 0
> +	li	s7, 0
> +	li	s8, 0
> +	li	s9, 0
> +	li	s10, 0
> +	li	s11, 0
> +	li	t3, 0
> +	li	t4, 0
> +	li	t5, 0
> +	li	t6, 0
> +	csrw	sscratch, 0
> +
> +#ifdef CONFIG_FPU
> +	csrr	t0, misa
> +	andi	t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
> +	bnez	t0, .Lreset_regs_done
> +
> +	li	t1, SR_FS
> +	csrs	sstatus, t1
> +	fmv.s.x	f0, zero
> +	fmv.s.x	f1, zero
> +	fmv.s.x	f2, zero
> +	fmv.s.x	f3, zero
> +	fmv.s.x	f4, zero
> +	fmv.s.x	f5, zero
> +	fmv.s.x	f6, zero
> +	fmv.s.x	f7, zero
> +	fmv.s.x	f8, zero
> +	fmv.s.x	f9, zero
> +	fmv.s.x	f10, zero
> +	fmv.s.x	f11, zero
> +	fmv.s.x	f12, zero
> +	fmv.s.x	f13, zero
> +	fmv.s.x	f14, zero
> +	fmv.s.x	f15, zero
> +	fmv.s.x	f16, zero
> +	fmv.s.x	f17, zero
> +	fmv.s.x	f18, zero
> +	fmv.s.x	f19, zero
> +	fmv.s.x	f20, zero
> +	fmv.s.x	f21, zero
> +	fmv.s.x	f22, zero
> +	fmv.s.x	f23, zero
> +	fmv.s.x	f24, zero
> +	fmv.s.x	f25, zero
> +	fmv.s.x	f26, zero
> +	fmv.s.x	f27, zero
> +	fmv.s.x	f28, zero
> +	fmv.s.x	f29, zero
> +	fmv.s.x	f30, zero
> +	fmv.s.x	f31, zero
> +	csrw	fcsr, 0
> +#endif /* CONFIG_FPU */
> +.Lreset_regs_done:
> +	ret
> +END(reset_regs)
> +#endif /* CONFIG_M_MODE */
> +
>  __PAGE_ALIGNED_BSS
>  	/* Empty zero page */
>  	.balign PAGE_SIZE

-- 
Regards,
Atish
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Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-24  5:42 RISC-V nommu support v2 Christoph Hellwig
2019-06-24  5:42 ` [PATCH 01/17] mm: provide a print_vma_addr stub for !CONFIG_MMU Christoph Hellwig
2019-06-24  5:42 ` [PATCH 02/17] mm: stub out all of swapops.h " Christoph Hellwig
2019-06-24  5:42 ` [PATCH 03/17] mm/nommu: fix the MAP_UNINITIALIZED flag Christoph Hellwig
2019-06-24  5:42 ` [PATCH 04/17] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig
2019-06-24  5:42 ` [PATCH 05/17] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm Christoph Hellwig
2019-07-01 18:53   ` Atish Patra
2019-06-24  5:43 ` [PATCH 06/17] riscv: refactor the IPI code Christoph Hellwig
2019-06-24  5:43 ` [PATCH 07/17] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-07-01 18:37   ` Atish Patra
2019-06-24  5:43 ` [PATCH 08/17] riscv: improve the default power off implementation Christoph Hellwig
2019-07-01 21:07   ` Atish Patra
2019-06-24  5:43 ` [PATCH 09/17] riscv: provide a flat entry loader Christoph Hellwig
2019-06-24  5:43 ` [PATCH 10/17] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-07-01 21:15   ` Atish Patra
2019-06-24  5:43 ` [PATCH 11/17] riscv: provide native clint access for M-mode Christoph Hellwig
2019-06-24  5:43 ` [PATCH 12/17] riscv: implement remote sfence.i natively " Christoph Hellwig
2019-06-24  5:43 ` [PATCH 13/17] riscv: poison SBI calls " Christoph Hellwig
2019-06-24  5:43 ` [PATCH 14/17] riscv: don't allow selecting SBI-based drivers " Christoph Hellwig
2019-06-24  5:43 ` [PATCH 15/17] riscv: use the correct interrupt levels " Christoph Hellwig
2019-06-24  5:43 ` [PATCH 16/17] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-07-01 21:26   ` Atish Patra [this message]
2019-07-08  8:26     ` Palmer Dabbelt
2019-08-13 15:40       ` Christoph Hellwig
2019-08-13 15:37     ` hch
2019-06-24  5:43 ` [PATCH 17/17] riscv: add nommu support Christoph Hellwig
2019-07-12 14:52   ` Vladimir Murzin
2019-06-24 11:47 ` RISC-V nommu support v2 Vladimir Murzin
2019-06-24 11:54   ` Christoph Hellwig
2019-06-24 13:08     ` Vladimir Murzin
2019-06-24 13:16       ` Christoph Hellwig
2019-06-25  7:31       ` Palmer Dabbelt
2019-06-25 12:37         ` Vladimir Murzin
2019-07-01  6:56 ` Christoph Hellwig
2019-07-01 16:06   ` Paul Walmsley

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