From: Vladimir Murzin <vladimir.murzin@arm.com>
To: Christoph Hellwig <hch@lst.de>,
Palmer Dabbelt <palmer@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>
Cc: linux-mm@kvack.org, Damien Le Moal <damien.lemoal@wdc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 17/17] riscv: add nommu support
Date: Fri, 12 Jul 2019 15:52:21 +0100 [thread overview]
Message-ID: <7b382b7a-41b6-62a5-02ab-189b3da9df70@arm.com> (raw)
In-Reply-To: <20190624054311.30256-18-hch@lst.de>
Hi Christoph,
On 6/24/19 6:43 AM, Christoph Hellwig wrote:
> The kernel runs in M-mode without using page tables, and thus can't run
> bare metal without help from additional firmware.
>
> Most of the patch is just stubbing out code not needed without page
> tables, but there is an interesting detail in the signals implementation:
>
> - The normal RISC-V syscall ABI only implements rt_sigreturn as VDSO
> entry point, but the ELF VDSO is not supported for nommu Linux.
> We instead copy the code to call the syscall onto the stack.
>
> In addition to enabling the nommu code a new defconfig for a small
> kernel image that can run in nommu mode on qemu is also provided, to run
> a kernel in qemu you can use the following command line:
>
> qemu-system-riscv64 -smp 2 -m 64 -machine virt -nographic \
> -kernel arch/riscv/boot/loader \
> -drive file=rootfs.ext2,format=raw,id=hd0 \
> -device virtio-blk-device,drive=hd0
>
> Contains contributions from Damien Le Moal <Damien.LeMoal@wdc.com>.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
> arch/riscv/Kconfig | 24 +++++---
> arch/riscv/configs/nommu_virt_defconfig | 78 +++++++++++++++++++++++++
> arch/riscv/include/asm/elf.h | 4 +-
> arch/riscv/include/asm/futex.h | 6 ++
> arch/riscv/include/asm/io.h | 4 ++
> arch/riscv/include/asm/mmu.h | 3 +
> arch/riscv/include/asm/page.h | 12 +++-
> arch/riscv/include/asm/pgalloc.h | 2 +
> arch/riscv/include/asm/pgtable.h | 38 ++++++++----
> arch/riscv/include/asm/tlbflush.h | 7 ++-
> arch/riscv/include/asm/uaccess.h | 4 ++
> arch/riscv/kernel/Makefile | 3 +-
> arch/riscv/kernel/entry.S | 11 ++++
> arch/riscv/kernel/head.S | 6 ++
> arch/riscv/kernel/signal.c | 17 +++++-
> arch/riscv/lib/Makefile | 8 +--
> arch/riscv/mm/Makefile | 3 +-
> arch/riscv/mm/cacheflush.c | 2 +
> arch/riscv/mm/context.c | 2 +
> arch/riscv/mm/init.c | 2 +
> 20 files changed, 200 insertions(+), 36 deletions(-)
> create mode 100644 arch/riscv/configs/nommu_virt_defconfig
>
snip...
>
> diff --git a/arch/riscv/configs/nommu_virt_defconfig b/arch/riscv/configs/nommu_virt_defconfig
> new file mode 100644
> index 000000000000..cf74e179bf90
> --- /dev/null
> +++ b/arch/riscv/configs/nommu_virt_defconfig
> @@ -0,0 +1,78 @@
> +# CONFIG_CPU_ISOLATION is not set
> +CONFIG_LOG_BUF_SHIFT=16
> +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=12
> +CONFIG_BLK_DEV_INITRD=y
> +# CONFIG_RD_BZIP2 is not set
> +# CONFIG_RD_LZMA is not set
> +# CONFIG_RD_XZ is not set
> +# CONFIG_RD_LZO is not set
> +# CONFIG_RD_LZ4 is not set
> +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> +CONFIG_EXPERT=y
> +# CONFIG_SYSFS_SYSCALL is not set
> +# CONFIG_FHANDLE is not set
> +# CONFIG_BASE_FULL is not set
> +# CONFIG_EPOLL is not set
> +# CONFIG_SIGNALFD is not set
> +# CONFIG_TIMERFD is not set
> +# CONFIG_EVENTFD is not set
> +# CONFIG_AIO is not set
> +# CONFIG_IO_URING is not set
> +# CONFIG_ADVISE_SYSCALLS is not set
> +# CONFIG_MEMBARRIER is not set
> +# CONFIG_KALLSYMS is not set
> +# CONFIG_VM_EVENT_COUNTERS is not set
> +# CONFIG_COMPAT_BRK is not set
> +CONFIG_SLOB=y
> +# CONFIG_SLAB_MERGE_DEFAULT is not set
> +# CONFIG_MMU is not set
> +CONFIG_MAXPHYSMEM_2GB=y
> +CONFIG_SMP=y
> +CONFIG_CMDLINE="root=/dev/vda rw earlycon=uart8250,mmio,0x10000000,115200n8 console=ttyS0"
> +CONFIG_CMDLINE_FORCE=y
> +# CONFIG_BLK_DEV_BSG is not set
> +CONFIG_PARTITION_ADVANCED=y
> +# CONFIG_MSDOS_PARTITION is not set
> +# CONFIG_EFI_PARTITION is not set
> +# CONFIG_MQ_IOSCHED_DEADLINE is not set
> +# CONFIG_MQ_IOSCHED_KYBER is not set
> +CONFIG_BINFMT_FLAT=y
IIUC, RISC-V requires stack pointer to be 16 byte aligned, but flat loader would
align stack pointer to max(sizeof(void *), ARCH_SLAB_MINALIGN). So, I think you
might want to define ARCH_SLAB_MINALIGN.
Cheers
Vladimir
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-07-12 14:52 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-24 5:42 RISC-V nommu support v2 Christoph Hellwig
2019-06-24 5:42 ` [PATCH 01/17] mm: provide a print_vma_addr stub for !CONFIG_MMU Christoph Hellwig
2019-06-24 5:42 ` [PATCH 02/17] mm: stub out all of swapops.h " Christoph Hellwig
2019-06-24 5:42 ` [PATCH 03/17] mm/nommu: fix the MAP_UNINITIALIZED flag Christoph Hellwig
2019-06-24 5:42 ` [PATCH 04/17] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig
2019-06-24 5:42 ` [PATCH 05/17] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm Christoph Hellwig
2019-07-01 18:53 ` Atish Patra
2019-06-24 5:43 ` [PATCH 06/17] riscv: refactor the IPI code Christoph Hellwig
2019-06-24 5:43 ` [PATCH 07/17] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-07-01 18:37 ` Atish Patra
2019-06-24 5:43 ` [PATCH 08/17] riscv: improve the default power off implementation Christoph Hellwig
2019-07-01 21:07 ` Atish Patra
2019-06-24 5:43 ` [PATCH 09/17] riscv: provide a flat entry loader Christoph Hellwig
2019-06-24 5:43 ` [PATCH 10/17] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-07-01 21:15 ` Atish Patra
2019-06-24 5:43 ` [PATCH 11/17] riscv: provide native clint access for M-mode Christoph Hellwig
2019-06-24 5:43 ` [PATCH 12/17] riscv: implement remote sfence.i natively " Christoph Hellwig
2019-06-24 5:43 ` [PATCH 13/17] riscv: poison SBI calls " Christoph Hellwig
2019-06-24 5:43 ` [PATCH 14/17] riscv: don't allow selecting SBI-based drivers " Christoph Hellwig
2019-06-24 5:43 ` [PATCH 15/17] riscv: use the correct interrupt levels " Christoph Hellwig
2019-06-24 5:43 ` [PATCH 16/17] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-07-01 21:26 ` Atish Patra
2019-07-08 8:26 ` Palmer Dabbelt
2019-08-13 15:40 ` Christoph Hellwig
2019-08-13 15:37 ` hch
2019-06-24 5:43 ` [PATCH 17/17] riscv: add nommu support Christoph Hellwig
2019-07-12 14:52 ` Vladimir Murzin [this message]
2019-06-24 11:47 ` RISC-V nommu support v2 Vladimir Murzin
2019-06-24 11:54 ` Christoph Hellwig
2019-06-24 13:08 ` Vladimir Murzin
2019-06-24 13:16 ` Christoph Hellwig
2019-06-25 7:31 ` Palmer Dabbelt
2019-06-25 12:37 ` Vladimir Murzin
2019-07-01 6:56 ` Christoph Hellwig
2019-07-01 16:06 ` Paul Walmsley
-- strict thread matches above, loose matches on Subject: below --
2019-06-10 22:16 RISC-V nommu support Christoph Hellwig
2019-06-10 22:16 ` [PATCH 17/17] riscv: add " Christoph Hellwig
2019-06-11 10:32 ` Vladimir Murzin
2019-06-11 12:44 ` David Hildenbrand
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=7b382b7a-41b6-62a5-02ab-189b3da9df70@arm.com \
--to=vladimir.murzin@arm.com \
--cc=damien.lemoal@wdc.com \
--cc=hch@lst.de \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mm@kvack.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@sifive.com \
--cc=paul.walmsley@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).