From: <Conor.Dooley@microchip.com>
To: <jernej.skrabec@gmail.com>, <samuel@sholland.org>,
<palmer@dabbelt.com>, <geert+renesas@glider.be>
Cc: <wens@csie.org>, <linux-sunxi@lists.linux.dev>,
<paul.walmsley@sifive.com>, <aou@eecs.berkeley.edu>,
<linux-riscv@lists.infradead.org>, <robh+dt@kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>
Subject: Re: [PATCH 00/12] riscv: Allwinner D1 platform support
Date: Wed, 7 Sep 2022 20:43:10 +0000 [thread overview]
Message-ID: <84f28dc3-3b65-ea70-4fa4-765d0c773c28@microchip.com> (raw)
In-Reply-To: <7423117.EvYhyI6sBW@kista>
On 06/09/2022 21:29, Jernej Škrabec wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Dne četrtek, 01. september 2022 ob 20:10:13 CEST je Palmer Dabbelt napisal(a):
>> On Sun, 14 Aug 2022 22:08:03 PDT (-0700), samuel@sholland.org wrote:
>>> This series adds the Kconfig/defconfig plumbing and devicetrees for a
>>> range of Allwinner D1-based boards. Many features are already enabled,
>>> including USB, Ethernet, and WiFi.
>>>
>>> The SoC devicetree uses bindings from the following series which have
>>> not yet been merged:
>>>
>>> - SRAM controller:
>>> https://lore.kernel.org/lkml/20220815041248.53268-1-samuel@sholland.org/
>>>
>>> - NVMEM cell bits property change:
>>> https://lore.kernel.org/lkml/20220814173656.11856-1-samuel@sholland.org/
>>>
>>> - In-package LDO regulators:
>>> https://lore.kernel.org/lkml/20220815043436.20170-1-samuel@sholland.org/
>>>
>>> All three of these are required to set the correct I/O domain voltages
>>> in the pin controller, which I would consider important to have in the
>>> initial version of the devicetree.
>>>
>>> The SoC devicetree does contain one small hack to avoid a dependency on
>>> the audio codec binding, since that is not ready yet: the codec node
>>> uses a bare "simple-mfd", "syscon" compatible.
>>>
>>> Samuel Holland (12):
>>> MAINTAINERS: Match the sun20i family of Allwinner SoCs
>>> dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles
>>> dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors
>>> dt-bindings: riscv: Add Allwinner D1 board compatibles
>>> riscv: Add the Allwinner SoC family Kconfig option
>>> riscv: dts: allwinner: Add the D1 SoC base devicetree
>>> riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree
>>> riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees
>>> riscv: dts: allwinner: Add MangoPi MQ Pro devicetree
>>> riscv: dts: allwinner: Add Dongshan Nezha STU devicetree
>>> riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees
>>> riscv: defconfig: Enable the Allwinner D1 platform and drivers
>>>
>>> .../devicetree/bindings/riscv/cpus.yaml | 2 +
>>> .../devicetree/bindings/riscv/sunxi.yaml | 64 ++
>>> .../devicetree/bindings/vendor-prefixes.yaml | 4 +
>>> MAINTAINERS | 2 +-
>>> arch/riscv/Kconfig.socs | 9 +
>>> arch/riscv/boot/dts/Makefile | 1 +
>>> arch/riscv/boot/dts/allwinner/Makefile | 10 +
>>> .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 242 +++++
>>> .../sun20i-d1-common-regulators.dtsi | 51 +
>>> .../dts/allwinner/sun20i-d1-devterm-v3.14.dts | 37 +
>>> .../sun20i-d1-dongshan-nezha-stu.dts | 114 +++
>>> .../sun20i-d1-lichee-rv-86-panel-480p.dts | 29 +
>>> .../sun20i-d1-lichee-rv-86-panel-720p.dts | 10 +
>>> .../sun20i-d1-lichee-rv-86-panel.dtsi | 92 ++
>>> .../allwinner/sun20i-d1-lichee-rv-dock.dts | 74 ++
>>> .../dts/allwinner/sun20i-d1-lichee-rv.dts | 84 ++
>>> .../allwinner/sun20i-d1-mangopi-mq-pro.dts | 128 +++
>>> .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 ++++
>>> arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 ++++++++++++++++++
>>> arch/riscv/configs/defconfig | 23 +-
>>> 20 files changed, 2045 insertions(+), 2 deletions(-)
>>> create mode 100644 Documentation/devicetree/bindings/riscv/sunxi.yaml
>>> create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
>>> create mode 100644
>>> arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts create
>>> mode 100644
>>> arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi create
>>> mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
>>> create mode 100644
>>> arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts create
>>> mode 100644
>>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
>>> create mode 100644
>>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
>>> create mode 100644
>>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi create
>>> mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
>>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
>>> create mode 100644
>>> arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts create mode
>>> 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts create mode
>>> 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
>>
>> I'm assuming these are aimed at the RISC-V tree? I'm generally OK with
>> that, though the DT folks have pointed out a handful of issues that look
>> pretty reasonable to me.
>
> DT changes for Allwinner ARM SoCs go trough sunxi tree. Should this be handled
> differently for RISC-V?
Microchip RISC-V DT go via a Microchip tree to Palmer. The other stuff gets
picked directly by him as it has no clear "owner". I think it would be nice
to be consistent for the new {renesas,sunxi} stuff and send those via vendor
trees to Palmer too. Just my 2 cents...
Conor.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-09-07 20:43 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-15 5:08 [PATCH 00/12] riscv: Allwinner D1 platform support Samuel Holland
2022-08-15 5:08 ` [PATCH 01/12] MAINTAINERS: Match the sun20i family of Allwinner SoCs Samuel Holland
2022-08-15 17:06 ` Heiko Stübner
2022-08-15 5:08 ` [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles Samuel Holland
2022-08-15 17:07 ` Heiko Stübner
2022-08-16 17:34 ` Rob Herring
2022-11-04 2:57 ` Icenowy Zheng
2022-11-20 11:23 ` Conor Dooley
2022-11-20 11:25 ` Conor Dooley
2022-08-15 5:08 ` [PATCH 03/12] dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors Samuel Holland
2022-08-15 17:12 ` Heiko Stübner
2022-08-16 17:34 ` Rob Herring
2022-08-15 5:08 ` [PATCH 04/12] dt-bindings: riscv: Add Allwinner D1 board compatibles Samuel Holland
2022-08-16 7:39 ` Krzysztof Kozlowski
2022-08-16 9:02 ` Heiko Stübner
2022-08-16 9:12 ` Heiko Stübner
2022-08-16 17:35 ` Rob Herring
2022-08-15 5:08 ` [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option Samuel Holland
2022-08-15 16:56 ` Conor.Dooley
2022-08-16 9:17 ` Heiko Stübner
2022-08-16 9:23 ` Conor.Dooley
2022-08-15 17:13 ` Heiko Stübner
2022-08-15 5:08 ` [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree Samuel Holland
2022-08-15 13:11 ` Andre Przywara
2022-08-15 17:01 ` Conor.Dooley
2022-08-20 17:24 ` Samuel Holland
2022-08-20 17:29 ` Conor.Dooley
2022-08-21 6:45 ` Icenowy Zheng
2022-08-21 10:04 ` Conor.Dooley
2022-08-22 11:46 ` Geert Uytterhoeven
2022-08-22 12:13 ` Conor.Dooley
2022-08-22 12:29 ` Andre Przywara
2022-08-22 12:31 ` Geert Uytterhoeven
2022-08-22 13:56 ` Conor.Dooley
2022-08-22 15:29 ` Jessica Clarke
2022-09-09 3:42 ` Samuel Holland
2022-09-09 7:10 ` Geert Uytterhoeven
2022-09-21 7:49 ` Geert Uytterhoeven
2022-08-22 10:50 ` Andre Przywara
2022-08-16 7:41 ` Krzysztof Kozlowski
2022-08-16 7:49 ` Jernej Škrabec
2022-08-16 9:12 ` Heiko Stübner
2022-08-16 9:25 ` Jernej Škrabec
2022-08-16 9:42 ` Krzysztof Kozlowski
2022-08-16 11:00 ` Andre Przywara
2022-08-16 11:11 ` Krzysztof Kozlowski
2022-08-16 11:12 ` Krzysztof Kozlowski
2022-08-16 11:34 ` Conor.Dooley
2022-08-22 11:40 ` Geert Uytterhoeven
2022-08-16 9:11 ` Heiko Stübner
2022-08-17 8:29 ` Krzysztof Kozlowski
2022-08-19 22:19 ` Conor.Dooley
2022-08-15 5:08 ` [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree Samuel Holland
2022-08-15 17:37 ` Conor.Dooley
2022-08-15 18:34 ` Conor.Dooley
2022-08-16 8:55 ` Heiko Stübner
2022-08-19 22:10 ` Conor.Dooley
2022-08-21 7:06 ` Icenowy Zheng
2022-09-04 20:10 ` Peter Korsgaard
2022-09-09 4:37 ` Samuel Holland
2022-09-09 7:18 ` Conor.Dooley
2022-09-09 8:11 ` Heiko Stübner
2022-09-09 19:04 ` Jessica Clarke
2022-09-03 15:21 ` Peter Korsgaard
2022-08-15 5:08 ` [PATCH 08/12] riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees Samuel Holland
2022-08-15 5:08 ` [PATCH 09/12] riscv: dts: allwinner: Add MangoPi MQ Pro devicetree Samuel Holland
2022-08-15 5:08 ` [PATCH 10/12] riscv: dts: allwinner: Add Dongshan Nezha STU devicetree Samuel Holland
2022-08-15 5:08 ` [PATCH 11/12] riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees Samuel Holland
2022-08-15 5:08 ` [PATCH 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers Samuel Holland
2022-08-15 7:05 ` [PATCH 00/12] riscv: Allwinner D1 platform support Conor.Dooley
2022-08-15 17:12 ` Conor.Dooley
2022-08-16 2:42 ` Samuel Holland
2022-08-16 6:38 ` Conor.Dooley
2022-09-01 18:10 ` Palmer Dabbelt
2022-09-02 5:42 ` Conor.Dooley
2022-09-06 20:29 ` Jernej Škrabec
2022-09-07 20:43 ` Conor.Dooley [this message]
2022-09-08 7:00 ` Geert Uytterhoeven
2022-09-08 9:04 ` Arnd Bergmann
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=84f28dc3-3b65-ea70-4fa4-765d0c773c28@microchip.com \
--to=conor.dooley@microchip.com \
--cc=aou@eecs.berkeley.edu \
--cc=devicetree@vger.kernel.org \
--cc=geert+renesas@glider.be \
--cc=jernej.skrabec@gmail.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=linux-sunxi@lists.linux.dev \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=samuel@sholland.org \
--cc=wens@csie.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).