From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA4E2C282C4 for ; Sat, 9 Feb 2019 16:12:01 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AA543218D2 for ; Sat, 9 Feb 2019 16:12:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Ti5aD62y" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AA543218D2 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=iGsvABFYZi6oFuRpu/nhAyBHzZpPRSQCDvXsIJI9MDU=; b=Ti5aD62yKh4BMF 1EYBZZEtsOcaS6BGXZQly2pcpqXyf125MIFe28tIlx8bOHvr4P7gp5DaKyNm0C0MpcsIISzdPTeql gPHOK5j93ZcL0P1mZvx8sYGm03Z6IEPRetF1uaW8QML95gcpBzsYpQXM7VMNdueXUkwJCuRyJ3Ae4 6eL8qhYad3yX5WxQAiH0+zXX37317NY7vYngXwDBxWBQ498ZQfdpaIC6Ezt1d5S/qXX89oULVkAp+ Lb8eRAF0phty9OMe01Z4I7nCH05sILi4D21KeHEKjZBrrNUUqj4tpou2c7dcHp2XTKEwr/EUr/nJc Q5rc00EMSnqVoMJ0xD8Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gsVEV-0004cm-NF; Sat, 09 Feb 2019 16:11:59 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gsVES-0004c7-EH for linux-riscv@lists.infradead.org; Sat, 09 Feb 2019 16:11:58 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B0663A78; Sat, 9 Feb 2019 08:11:53 -0800 (PST) Received: from big-swifty.misterjones.org (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 129FE3F589; Sat, 9 Feb 2019 08:11:43 -0800 (PST) Date: Sat, 09 Feb 2019 16:11:42 +0000 Message-ID: <86bm3lt001.wl-marc.zyngier@arm.com> From: Marc Zyngier To: David Abdurachmanov Subject: Re: [v3 PATCH 8/8] RISC-V: Assign hwcap only according to boot cpu. In-Reply-To: References: <1549590681-24125-1-git-send-email-atish.patra@wdc.com> <1549590681-24125-9-git-send-email-atish.patra@wdc.com> <20190208091133.GD16932@infradead.org> <8f5fd0c8-0320-00b1-4ddf-b1225be352c8@wdc.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190209_081156_497151_1E2EF2C8 X-CRM114-Status: GOOD ( 27.58 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Albert Ou , Jason Cooper , Alan Kao , Dmitriy Cherkasov , Anup Patel , Daniel Lezcano , Patrick =?UTF-8?B?U3TDpGhsaW4=?= , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Palmer Dabbelt , Paul Walmsley , Andreas Schwab , "linux-riscv@lists.infradead.org" , Thomas Gleixner , Zong Li Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Sat, 09 Feb 2019 04:26:07 +0000, David Abdurachmanov wrote: > > On Sat, Feb 9, 2019 at 12:03 AM Atish Patra wrote: > > > > On 2/8/19 1:11 AM, Christoph Hellwig wrote: > > >> + * We don't support running Linux on hertergenous ISA systems. > > >> + * But first "okay" processor might not be the boot cpu. > > >> + * Check the ISA of boot cpu. > > > > > > Please use up your available 80 characters per line in comments. > > > > > I will fix it. > > > > >> + /* > > >> + * All "okay" hart should have same isa. We don't know how to > > >> + * handle if they don't. Throw a warning for now. > > >> + */ > > >> + if (elf_hwcap && temp_hwcap != elf_hwcap) > > >> + pr_warn("isa mismatch: 0x%lx != 0x%lx\n", > > >> + elf_hwcap, temp_hwcap); > > >> + > > >> + if (hartid == boot_cpu_hartid) > > >> + boot_hwcap = temp_hwcap; > > >> + elf_hwcap = temp_hwcap; > > > > > > So we always set elf_hwcap to the capabilities of the previous cpu. > > > > > >> + temp_hwcap = 0; > > > > > > I think tmp_hwcap should be declared and initialized inside the outer loop > > > instead having to manually reset it like this. > > > > > >> + } > > >> > > >> + elf_hwcap = boot_hwcap; > > > > > > And then reset it here to the boot cpu. > > > > > > Shoudn't we only report the features supported by all cores? Otherwise > > > we'll still have problems if the boot cpu supports a feature, but not > > > others. > > > > > > > Hmm. The other side of the argument is boot cpu does have a feature that > > is not supported by other hart that didn't even boot. > > The user space may execute something based on boot cpu capability but > > that won't be enabled. > > > > At least, in this way we know that we are compatible completely with > > boot cpu capabilities. Thoughts ? > > There is one example on the market, e.g., Samsung Exynos 9810. > > Mongoose 3 (big cores) only support ARMv8.0, while Cortex-A55 > (little ones) support ARMv8.2 (and that brings atomics support). > I think, it's the only ARM SOC that supports different ISA extensions > between cores on the same package. > > Kernel scheduler doesn't know that big cores are missing atomics > support or that applications needs it and moves the thread > resulting in illegal instruction. Not quite. The scheduler doesn't have to know (thankfully). The problem is that the Samsung folks tampered with the detection logic in the kernel, and ended up advertising the LSE atomics to userspace (despite only being available on half the cores). If you run a mainline kernel on this things, it will just work, as the LSE atomics are not advertised to userspace at all. > > E.g., see Golang issue: https://github.com/golang/go/issues/28431 > > I also recall Jon Masters (Computer Architect at Red Hat) advocating > against having cores with mismatched capabilities on the server > market. Well, nobody recommends that, server or not. That being said, it is possible to handle it, and the arm64 kernel has been dealing with such thing from day 1. We can have CPUs with different PMUs, implemented page sizes, VA and PA spaces... What it takes is some work in the kernel to sanitize it, and be careful in what you expose to userspace. The thing to realise is that people will build stupid systems, no matter how loud you shout. You can either pretend they don't exist, or try to deal with them. Thanks, M. -- Jazz is not dead, it just smell funny. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv