From: Marc Zyngier <maz@kernel.org>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Atish Patra <atishp@atishpatra.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v11 3/7] genirq: Add mechanism to multiplex a single HW IPI
Date: Sat, 26 Nov 2022 14:28:14 +0000 [thread overview]
Message-ID: <87sfi5u6wx.wl-maz@kernel.org> (raw)
In-Reply-To: <CAK9=C2UeMVnMBKOgO_nseUZnmvG+CUu7xaRXtt6j3Esr+ap04g@mail.gmail.com>
On Sat, 26 Nov 2022 13:31:46 +0000,
Anup Patel <apatel@ventanamicro.com> wrote:
>
> On Sat, Nov 26, 2022 at 6:12 PM Marc Zyngier <maz@kernel.org> wrote:
> >
> > On Mon, 14 Nov 2022 09:39:00 +0000,
> > Anup Patel <apatel@ventanamicro.com> wrote:
> > >
> > > +struct ipi_mux_control {
> > > + void *data;
> > > + unsigned int nr;
> >
> > Honestly, I think we can get rid of this. The number of IPIs Linux
> > uses is pretty small, and assuming a huge value (like 32) would be
> > enough. It would save looking up this value on each IPI handling.
>
> I had kept in-case some driver wanted to create fewer (< 32)
> muxed IPIs.
I'm fine with being able to specifying the max, but I'm not sure there
is a need to keep track of it any further. Certainly, the overhead of
loading this value on each IPI could be removed. On most architecture,
for_each_set_bit() and co and better optimised with a fixed number of
bits.
> > > +static const struct irq_chip ipi_mux_chip = {
> > > + .name = "IPI Mux",
> > > + .irq_mask = ipi_mux_mask,
> > > + .irq_unmask = ipi_mux_unmask,
> > > + .ipi_send_mask = ipi_mux_send_mask,
> > > +};
> >
> > I really think this could either be supplied by the irqchip, or
> > somehow patched to avoid the pointless imux->ops->ipi_mux_send
> > indirection. Pointer chasing hurts.
>
> Once we remove ipi_mux_pre/post_handle() callbacks, the
> "ops" will be pointless and we will be able to remove one level
> of indirection here.
>
> We certainly need a mux irqchip to implement the
> mask/unmask semantics for muxed IPIs.
I'm not disputing that last point.
> > > +/**
> > > + * ipi_mux_create - Create virtual IPIs multiplexed on top of a single
> > > + * parent IPI.
> > > + * @parent_virq: virq of the parent per-CPU IRQ
> > > + * @nr_ipi: number of virtual IPIs to create. This should
> > > + * be <= BITS_PER_TYPE(int)
> > > + * @ops: multiplexing operations for the parent IPI
> > > + * @data: opaque data used by the multiplexing operations
> >
> > What is the use for data? If anything, that data should be passed via
> > the mux interrupt. But the whole point of this is to make the mux
> > invisible. So this whole 'data' business is a mystery to me.
>
> This is added only to pass back driver data in ipi_mux_send().
Again, what is the purpose of such data? If you need per-interrupt
data, this should be provided by the requester of the interrupt.
M.
--
Without deviation from the norm, progress is not possible.
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next prev parent reply other threads:[~2022-11-26 14:28 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-14 9:38 [PATCH v11 0/7] RISC-V IPI Improvements Anup Patel
2022-11-14 9:38 ` [PATCH v11 1/7] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel
2022-11-14 9:38 ` [PATCH v11 2/7] irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode Anup Patel
2022-11-14 9:39 ` [PATCH v11 3/7] genirq: Add mechanism to multiplex a single HW IPI Anup Patel
2022-11-26 12:42 ` Marc Zyngier
2022-11-26 13:31 ` Anup Patel
2022-11-26 14:28 ` Marc Zyngier [this message]
2022-11-26 16:00 ` Anup Patel
2022-11-14 9:39 ` [PATCH v11 4/7] RISC-V: Treat IPIs as normal Linux IRQs Anup Patel
2022-11-14 9:39 ` [PATCH v11 5/7] RISC-V: Allow marking IPIs as suitable for remote FENCEs Anup Patel
2022-11-14 9:39 ` [PATCH v11 6/7] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel
2022-11-14 9:39 ` [PATCH v11 7/7] RISC-V: Use IPIs for remote icache " Anup Patel
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