messages from 2019-03-25 06:57:37 to 2019-04-06 23:14:41 UTC [more...]
[PATCH 0/7] arch: riscv: add DT file support, starting with the SiFive HiFive-U
2019-04-06 23:14 UTC (4+ messages)
` [PATCH 7/7] riscv: dts: add initial board data for the SiFive HiFive Unleashed
[PATCH] dt-bindings: clock: sifive: add FU540-C000 PRCI clock constants
2019-04-06 6:07 UTC (2+ messages)
[PATCH v3] RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systems
2019-04-05 21:17 UTC (4+ messages)
[PATCH v8 06/20] riscv: mm: Add p?d_large() definitions
2019-04-05 4:14 UTC (2+ messages)
[GIT PULL] RISC-V Patches for 5.1-rc4
2019-04-05 1:55 UTC (2+ messages)
[PATCH 3/6 v3] riscv: Fix syscall_get_arguments() and syscall_set_arguments()
2019-04-04 23:29 UTC (14+ messages)
` [PATCH 5/6 v3] syscalls: Remove start and number from syscall_get_arguments() args
` [PATCH 6/6 v3] syscalls: Remove start and number from syscall_set_arguments() args
[PATCH v2 0/5] Provide generic top-down mmap layout functions
2019-04-04 5:51 UTC (6+ messages)
` [PATCH v2 1/5] mm, fs: Move randomize_stack_top from fs to mm
` [PATCH v2 2/5] arm64, mm: Move generic mmap layout functions "
` [PATCH v2 3/5] arm: Use generic mmap top-down layout
` [PATCH v2 4/5] mips: "
` [PATCH v2 5/5] riscv: Make mmap allocation top-down by default
[PATCH 0/2] L2 Cache EDAC Support for HiFive Unleashed
2019-04-04 1:17 UTC (17+ messages)
` [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller
` [PATCH 2/2] sifive: edac: Add EDAC driver for Sifive l2 Cache Controller
Perf counters on SiFive FU540-C000
2019-04-03 22:15 UTC (7+ messages)
[PATCH v2] RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systems
2019-04-03 14:46 UTC (2+ messages)
RISC-V OpenSBI Mailing List
2019-04-03 10:34 UTC
UNIX-Class Platform Specification Working Group
2019-04-03 4:48 UTC (9+ messages)
` [isa-dev] "
` [hw-dev] "
[isa-dev] UNIX-Class Platform Specification Working Group
2019-04-03 1:53 UTC
[hw-dev] UNIX-Class Platform Specification Working Group
2019-04-03 1:53 UTC
[PATCH] RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systems
2019-04-02 10:14 UTC (5+ messages)
[PATCH 1/3] csky: Use in_syscall & forget_syscall instead of r11_sig
2019-04-02 8:02 UTC (3+ messages)
` [PATCH 2/3] csky: Reconstruct signal.c and entry.S
` [PATCH 3/3] riscv/signal: Fixup additional syscall restarting
lists.infradead.org mailing list memberships reminder
2019-04-01 12:00 UTC
[PATCH] riscv: fix syscall_get_arguments() and syscall_set_arguments()
2019-03-30 0:26 UTC (9+ messages)
[PATCH 0/2] EDAC Support for SiFive SoCs
2019-03-29 19:45 UTC (7+ messages)
` [PATCH 2/2] edac: sifive: Add EDAC driver for SiFive FU540-C000 chip
[PATCH] RISC-V: Use IS_ENABLED(CONFIG_CMODEL_MEDLOW)
2019-03-29 7:41 UTC (2+ messages)
[PATCH] RISC-V: Fix FIXMAP_TOP to avoid overlap with VMALLOC area
2019-03-29 7:08 UTC (4+ messages)
[PATCH v3 4/4] RISC-V: Allow booting kernel from any 4KB aligned address
2019-03-28 15:35 UTC
[PATCH v2] RISC-V: Implement ASID allocator
2019-03-29 5:12 UTC (10+ messages)
[PATCH v3] RISC-V: Implement ASID allocator
2019-03-29 4:51 UTC
[RFC][PATCH 3/4 v2] syscalls: Remove start and number from syscall_get_arguments() args
2019-03-28 23:05 UTC (2+ messages)
` [RFC][PATCH 4/4 v2] syscalls: Remove start and number from syscall_set_arguments() args
[PATCH 0/7] RISC-V: Sparsmem, Memory Hotplug and pte_devmap for P2P
2019-03-28 18:24 UTC (15+ messages)
` [PATCH 1/7] RISC-V: Implement sparsemem
` [PATCH 2/7] RISC-V: doc: Add file describing the virtual memory map
` [PATCH 3/7] RISC-V: Rework kernel's virtual address space mapping
` [PATCH 4/7] RISC-V: Update page tables to cover the whole linear mapping
` [PATCH 5/7] RISC-V: Implement memory hotplug
` [PATCH 6/7] RISC-V: Implement memory hot remove
` [PATCH 7/7] RISC-V: Implement pte_devmap()
[PATCH v4 0/5] TLB/I$ flush cleanups and improvements
2019-03-28 16:57 UTC (24+ messages)
` [PATCH v4 1/5] riscv: move flush_icache_{all,mm} to cacheflush.c
` [PATCH v4 3/5] riscv: fix sbi_remote_sfence_vma{,_asid}
` [PATCH v4 2/5] riscv: move switch_mm to its own file
` [PATCH v4 4/5] riscv: rewrite tlb flush for performance
` [PATCH v4 5/5] riscv: implement IPI-based remote TLB shootdown
[PATCH v7 06/20] riscv: mm: Add p?d_large() definitions
2019-03-28 15:20 UTC
[PATCH v3 0/4] Boot RISC-V kernel from any 4KB aligned address
2019-03-28 10:24 UTC (20+ messages)
` [PATCH v3 1/4] RISC-V: Add separate defconfig for 32bit systems
` [PATCH v3 2/4] RISC-V: Fix memory reservation in setup_bootmem()
` [PATCH v3 3/4] RISC-V: Remove redundant trampoline page table
` [PATCH v3 4/4] RISC-V: Allow booting kernel from any 4KB aligned address
[PATCH] RISC-V: Implement ASID allocator
2019-03-27 14:12 UTC (9+ messages)
[PATCH v11 0/2] PWM support for HiFive Unleashed
2019-03-27 9:04 UTC (7+ messages)
` [PATCH v11 1/2] pwm: sifive: Add DT documentation for SiFive PWM Controller
` [PATCH v11 2/2] pwm: sifive: Add a driver for SiFive SoC PWM
[PATCH v2] RISC-V: Always compile mm/init.c with cmodel=medany
2019-03-27 0:10 UTC (8+ messages)
[PATCH] irqchip: plic: Fix priority base offset
2019-03-26 22:26 UTC (5+ messages)
[PATCH v6 05/19] riscv: mm: Add p?d_large() definitions
2019-03-26 16:26 UTC
[PATCH v4] RISC-V: Always compile mm/init.c with cmodel=medany and notrace
2019-03-26 8:03 UTC
Thoughts on kexec / SBI
2019-03-26 6:57 UTC (4+ messages)
[PATCH 5.0 29/52] clocksource/drivers/riscv: Fix clocksource mask
2019-03-26 6:30 UTC
[PATCH v3] RISC-V: Always compile mm/init.c with cmodel=medany and notrace
2019-03-26 3:57 UTC (3+ messages)
[PATCH 0/3] RISC-V SBI earlycon
2019-03-25 16:23 UTC (2+ messages)
[PATCH v5 0/3] locking/rwsem: Rwsem rearchitecture part 0
2019-03-25 15:25 UTC (3+ messages)
` [PATCH v5 3/3] locking/rwsem: Optimize down_read_trylock()
[PATCH v9 0/2] PWM support for HiFive Unleashed
2019-03-25 12:09 UTC (8+ messages)
[PATCH v2 0/4] provide a generic free_initmem implementation
2019-03-25 7:20 UTC (2+ messages)
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