messages from 2019-04-12 14:40:52 to 2019-04-25 08:15:35 UTC [more...]
[PATCH v5 0/3] Allow accessing CSR using CSR number
2019-04-25 8:15 UTC (4+ messages)
` [PATCH v5 1/3] RISC-V: Use tabs to align macro values in asm/csr.h
` [PATCH v5 2/3] RISC-V: Add interrupt related SCAUSE defines "
` [PATCH v5 3/3] RISC-V: Access CSRs using CSR numbers
[PATCH v4 0/3] Allow accessing CSR using CSR number
2019-04-25 8:01 UTC (7+ messages)
` [PATCH v4 1/3] RISC-V: Use tabs to align macro values in asm/csr.h
` [PATCH v4 2/3] RISC-V: Add interrupt related SCAUSE defines "
` [PATCH v4 3/3] RISC-V: Access CSRs using CSR numbers
[PATCH 0/2] L2 cache controller support for SiFive FU540
2019-04-25 5:54 UTC (3+ messages)
` [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
` [PATCH 2/2] RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs
[PATCH v3] RISC-V: Implement ASID allocator
2019-04-25 5:55 UTC (7+ messages)
[PATCH v3 0/3] Allow accessing CSR using CSR number
2019-04-25 5:04 UTC (10+ messages)
` [PATCH v3 1/3] RISC-V: Use tabs to align macro values in asm/csr.h
` [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines "
` [PATCH v3 3/3] RISC-V: Access CSRs using CSR numbers
[PATCH 0/7] RISC-V: Sparsmem, Memory Hotplug and pte_devmap for P2P
2019-04-24 23:23 UTC (2+ messages)
[PATCH v4 0/4] Miscellaneous kernel command line fixes
2019-04-24 21:48 UTC (5+ messages)
` [PATCH 1/4] RISC-V: Add RISC-V specific arch_match_cpu_phys_id
` [PATCH 2/4] RISC-V: Implement nosmp commandline option
` [PATCH 3/4] RISC-V: Support nr_cpus command line option
` [PATCH 4/4] RISC-V: Fix minor checkpatch issues
[PATCH v3 2/4] RISC-V: Fix memory reservation in setup_bootmem()
2019-04-24 21:06 UTC (2+ messages)
[PATCH v5 0/2] tty: serial: add DT bindings and serial driver for the SiFive FU540 UART
2019-04-24 18:58 UTC (10+ messages)
` [PATCH v5 1/2] dt-bindings: serial: add documentation for the SiFive UART driver
` [PATCH v5 2/2] tty: serial: add driver for the SiFive UART
[PATCH v3 0/3] Miscellaneous kernel command line fixes
2019-04-24 16:50 UTC (9+ messages)
` [PATCH v3 1/3] RISC-V: Add RISC-V specific arch_match_cpu_phys_id
` [PATCH v3 2/3] RISC-V: Implement nosmp commandline option
` [PATCH v3 3/3] RISC-V: Support nr_cpus command line option
[PATCH AUTOSEL 4.19 14/52] riscv: fix accessing 8-byte variable from RV32
2019-04-24 14:38 UTC
[PATCH AUTOSEL 5.0 20/66] riscv: fix accessing 8-byte variable from RV32
2019-04-24 14:32 UTC
[PATCH] riscv: Support non-coherency memory model
2019-04-24 14:23 UTC (12+ messages)
[PATCH] RISC-V: redefine PTRS_PER_PGD/PTRS_PER_PMD/PTRS_PER_PTE
2019-04-24 8:13 UTC (2+ messages)
[PATCH] RISC-V: redefine PTRS_PER_PGD/PTRS_PER_PMD/PTRS_PER_PTE
2019-04-24 7:59 UTC (2+ messages)
[PATCH] riscv: vdso: drop unnecessary cc-ldoption
2019-04-24 6:20 UTC (2+ messages)
[PATCH] RISC-V: Add an Image header that boot loader can parse
2019-04-23 23:25 UTC
misc cleanups v3
2019-04-23 8:23 UTC (13+ messages)
` [PATCH 01/11] riscv: use asm-generic/extable.h
` [PATCH 02/11] riscv: turn mm_segment_t into a struct
` [PATCH 03/11] riscv: remove unreachable big endian code
` [PATCH 04/11] riscv: remove CONFIG_RISCV_ISA_A
` [PATCH 05/11] riscv: clear all pending interrupts when booting
` [PATCH 06/11] riscv: simplify the stack pointer setup in head.S
` [PATCH 07/11] riscv: cleanup the parse_dtb calling conventions
` [PATCH 08/11] riscv: remove unreachable !HAVE_FUNCTION_GRAPH_RET_ADDR_PTR code
` [PATCH 09/11] riscv: remove duplicate macros from ptrace.h
` [PATCH 10/11] riscv: print the unexpected interrupt cause
` [PATCH 11/11] riscv: call pm_power_off from machine_halt / machine_power_off
Testing the recent RISC-V DT patchsets
2019-04-23 0:17 UTC
[PATCH v3 00/11] Provide generic top-down mmap layout functions
2019-04-22 19:56 UTC (42+ messages)
` [PATCH v3 01/11] mm, fs: Move randomize_stack_top from fs to mm
` [PATCH v3 02/11] arm64: Make use of is_compat_task instead of hardcoding this test
` [PATCH v3 03/11] arm64: Consider stack randomization for mmap base only when necessary
` [PATCH v3 04/11] arm64, mm: Move generic mmap layout functions to mm
` [PATCH v3 05/11] arm: Properly account for stack randomization and stack guard gap
` [PATCH v3 06/11] arm: Use STACK_TOP when computing mmap base address
` [PATCH v3 07/11] arm: Use generic mmap top-down layout
` [PATCH v3 08/11] mips: Properly account for stack randomization and stack guard gap
` [PATCH v3 09/11] mips: Use STACK_TOP when computing mmap base address
` [PATCH v3 10/11] mips: Use generic mmap top-down layout
` [PATCH v3 11/11] riscv: Make mmap allocation top-down by default
[PATCH v2 00/79] Convert files to ReST
2019-04-22 14:51 UTC (4+ messages)
` [PATCH v2 18/79] docs: kbuild: convert docs to ReST and rename to *.rst
` [PATCH v2 29/79] docs: riscv: "
[PATCH v5 0/3] Add support for the Purism Librem5 devkit
2019-04-22 13:39 UTC (9+ messages)
` [PATCH v5 1/3] arm64: dts: fsl: librem5: Add a device tree for the "
` [PATCH v5 2/3] dt-bindings: Add an entry for Purism SPC
` [PATCH v5 3/3] dt-bindings: arm: fsl: Add the imx8mq boards
[PATCH 00/57] Convert files to ReST
2019-04-19 22:10 UTC (4+ messages)
` [PATCH 29/57] docs: riscv: convert it to ReST format
` Avoiding merge conflicts while adding new docs - Was: Re: [PATCH 00/57] Convert files to ReST
[PATCH 0/3] L2 cache controller and EDAC support for SiFive SoCs
2019-04-18 12:50 UTC (6+ messages)
` [PATCH 1/3] RISC-V: Add DT documentation for SiFive L2 Cache Controller
` [PATCH 2/3] RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs
` [PATCH 3/3] edac: sifive: Add EDAC platform "
[PATCH] RISC-V: redefine PTRS_PER_PGD/PTRS_PER_PMD/PTRS_PER_PTE
2019-04-18 6:13 UTC (2+ messages)
[GIT PULL] RISC-V Patches for 5.1-rc6
2019-04-16 21:30 UTC (2+ messages)
[RFT/RFC PATCH v3 0/5] Unify CPU topology across ARM & RISC-V
2019-04-16 19:04 UTC (13+ messages)
` [RFT/RFC PATCH v3 3/5] cpu-topology: Move cpu topology code to common code
` [RFT/RFC PATCH v3 4/5] arm: Use common cpu_topology
[PATCH] RISC-V: Add kexec support
2019-04-16 13:01 UTC
[PATCH] RISC-V: Add support for kexec on kexec-tools
2019-04-16 12:32 UTC
[PATCH 5.0 077/117] riscv: Fix syscall_get_arguments() and syscall_set_arguments()
2019-04-15 19:00 UTC
[PATCH 4.19 070/101] riscv: Fix syscall_get_arguments() and syscall_set_arguments()
2019-04-15 18:59 UTC
Patch "riscv: Fix syscall_get_arguments() and syscall_set_arguments()" has been added to the 5.0-stable tree
2019-04-15 12:14 UTC
Patch "riscv: Fix syscall_get_arguments() and syscall_set_arguments()" has been added to the 4.19-stable tree
2019-04-15 12:14 UTC
[PATCH v2 0/3] riscv: Add perf callchain support
2019-04-15 9:52 UTC (4+ messages)
` [PATCH v2 1/3] "
` [PATCH v2 2/3] riscv: Add support for perf registers sampling
` [PATCH v2 3/3] riscv: Add support for libdw
[PATCH v2 0/3] Allow accessing CSR using CSR number
2019-04-15 7:29 UTC (6+ messages)
` [PATCH v2 1/3] RISC-V: Add separate asm/encoding.h for spec related defines
` [PATCH v2 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/encoding.h
` [PATCH v2 3/3] RISC-V: Access CSRs using CSR numbers
[PATCH v11 0/2] PWM support for HiFive Unleashed
2019-04-15 6:06 UTC (2+ messages)
[0/3] TLB flush counters
2019-04-14 14:27 UTC (5+ messages)
` [1/3] x86: Update DEBUG_TLBFLUSH options description
[PATCH 0/3] Allow accessing CSR using CSR number
2019-04-13 8:15 UTC (10+ messages)
` [PATCH 1/3] RISC-V: Add separate asm/encoding.h for spec related defines
` [PATCH 2/3] RISC-V: Add defines for CSR numbers
` [PATCH 3/3] RISC-V: Access CSRs using "
misc cleanups v2
2019-04-12 16:09 UTC (4+ messages)
` [PATCH 11/12] riscv: print the unexpected interrupt cause
` [PATCH 12/12] riscv: call pm_power_off from machine_halt / machine_power_off
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