messages from 2019-04-22 19:54:45 to 2019-05-02 10:35:18 UTC [more...]
[PATCH v2 0/2] L2 cache controller support for SiFive FU540
2019-05-02 10:34 UTC
[PATCH v2 0/3] add support for is25wp256 spi-nor device
2019-05-02 9:56 UTC (10+ messages)
` [PATCH v2 1/3] mtd: spi-nor: add support for is25wp256
` [PATCH v2 2/3] mtd: spi-nor: add support to unlock flash device
` [PATCH v2 3/3] mtd: spi-nor: add locking support for is25xxxxx device
[PATCH 0/2] L2 cache controller support for SiFive FU540
2019-05-02 9:35 UTC (13+ messages)
` [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
` [PATCH 2/2] RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs
[PATCH v4 0/2] Two-stagged initial page table setup
2019-05-02 5:02 UTC (3+ messages)
` [PATCH v4 1/2] RISC-V: Fix memory reservation in setup_bootmem()
` [PATCH v4 2/2] RISC-V: Setup initial page tables in two stages
[PATCH v11 0/2] PWM support for HiFive Unleashed
2019-05-02 4:01 UTC (6+ messages)
[PATCH] RISC-V: Add an Image header that boot loader can parse
2019-05-01 20:32 UTC (11+ messages)
[v2 PATCH] RISC-V: Add a PE/COFF compliant Image header
2019-05-01 19:56 UTC
lists.infradead.org mailing list memberships reminder
2019-05-01 12:00 UTC
[PATCH] RISC-V: Avoid using invalid intermediate translations
2019-05-01 3:19 UTC (2+ messages)
[PATCH] tty: Don't force RISCV SBI console as preferred console
2019-05-01 0:25 UTC (8+ messages)
[PATCH v6 0/3] Allow accessing CSR using CSR number
2019-05-01 0:11 UTC (6+ messages)
` [PATCH v6 1/3] RISC-V: Use tabs to align macro values in asm/csr.h
` [PATCH v6 2/3] RISC-V: Add interrupt related SCAUSE defines "
` [PATCH v6 3/3] RISC-V: Access CSRs using CSR numbers
[PATCH v4 0/2] clk: add driver for the SiFive FU540 PRCI and PLLs it controls
2019-04-30 20:51 UTC (3+ messages)
` [PATCH v4 1/2] clk: analogbits: add Wide-Range PLL library
` [PATCH v4 2/2] clk: sifive: add a driver for the SiFive FU540 PRCI IP block
[PATCH v3 1/3] clk: analogbits: add Wide-Range PLL library
2019-04-30 20:22 UTC (19+ messages)
` [PATCH v3 2/3] dt-bindings: clk: add documentation for the SiFive PRCI driver
` [PATCH v3 3/3] clk: sifive: add a driver for the SiFive FU540 PRCI IP block
[PATCH] riscv: Support non-coherency memory model
2019-04-30 3:29 UTC (18+ messages)
` [tech-privileged] "
[PATCH v3 0/3] Miscellaneous kernel command line fixes
2019-04-30 0:36 UTC (11+ messages)
` [PATCH v3 1/3] RISC-V: Add RISC-V specific arch_match_cpu_phys_id
` [PATCH v3 2/3] RISC-V: Implement nosmp commandline option
` [PATCH v3 3/3] RISC-V: Support nr_cpus command line option
[PATCH] riscv: vdso: drop unnecessary cc-ldoption
2019-04-29 23:40 UTC (3+ messages)
[PATCH v2 0/3] TLB flush counters
2019-04-29 21:29 UTC (6+ messages)
` [PATCH v2 1/3] x86: Move DEBUG_TLBFLUSH option
` [PATCH v2 2/3] RISC-V: Enable TLBFLUSH counters for debug kernel
` [PATCH v2 3/3] RISC-V: Update tlb flush counters
[PATCH v3 0/3] TLB flush counters
2019-04-29 21:27 UTC (4+ messages)
` [PATCH v3 1/3] x86: Move DEBUG_TLBFLUSH option
` [PATCH v3 2/3] RISC-V: Enable TLBFLUSH counters for debug kernel
` [PATCH v3 3/3] RISC-V: Update tlb flush counters
[0/3] TLB flush counters
2019-04-29 19:52 UTC (7+ messages)
` [1/3] x86: Update DEBUG_TLBFLUSH options description
[PATCH 1/6] arch: riscv: add support for building DTB files from DT source data
2019-04-29 18:13 UTC (4+ messages)
` [PATCH 2/6] dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540
[PATCH 3/3] riscv: Add support for libdw
2019-04-29 8:45 UTC
[PATCH 2/3] riscv: Add support for perf registers sampling
2019-04-29 8:42 UTC
[PATCH 1/3] riscv: Add perf callchain support
2019-04-29 8:39 UTC
[PATCH v3 00/11] Provide generic top-down mmap layout functions
2019-04-28 14:27 UTC (10+ messages)
` [PATCH v3 04/11] arm64, mm: Move generic mmap layout functions to mm
` [PATCH v3 11/11] riscv: Make mmap allocation top-down by default
[RFT PATCH v4 0/5] Unify CPU topology across ARM & RISC-V
2019-04-28 0:25 UTC (6+ messages)
` [RFT PATCH v4 1/5] Documentation: DT: arm: add support for sockets defining package boundaries
` [RFT PATCH v4 2/5] dt-binding: cpu-topology: Move cpu-map to a common binding
` [RFT PATCH v4 3/5] cpu-topology: Move cpu topology code to common code
` [RFT PATCH v4 4/5] arm: Use common cpu_topology structure and functions
` [RFT PATCH v4 5/5] RISC-V: Parse cpu topology during boot
[2/3] RISC-V: Update tlb flush counters
2019-04-26 18:54 UTC (3+ messages)
[PATCH v3 0/3] clk: add driver for the SiFive FU540 PRCI and PLLs it controls
2019-04-26 17:17 UTC (4+ messages)
[PATCH 0/7] RISC-V: Sparsmem, Memory Hotplug and pte_devmap for P2P
2019-04-26 16:37 UTC (3+ messages)
[PATCH v5 0/2] tty: serial: add DT bindings and serial driver for the SiFive FU540 UART
2019-04-26 16:36 UTC (8+ messages)
` [PATCH v5 1/2] dt-bindings: serial: add documentation for the SiFive UART driver
[RFC][PATCH] RISC-V: Add kexec support
2019-04-26 3:25 UTC (5+ messages)
misc cleanups v3
2019-04-25 21:58 UTC (3+ messages)
misc cleanups
2019-04-25 20:05 UTC (11+ messages)
` [PATCH 1/9] riscv: use asm-generic/extable.h
` [PATCH 7/9] riscv: remove duplicate macros from ptrace.h
` [PATCH 8/9] riscv: print the unexpected interrupt cause
` [PATCH 9/9] riscv: call pm_power_off from machine_halt / machine_power_off
[PATCH v2 2/2] riscv: Introduce huge page support for 32/64bit kernel
2019-04-25 18:52 UTC (3+ messages)
[PATCH 3/3] riscv/signal: Fixup additional syscall restarting
2019-04-25 18:11 UTC (2+ messages)
[PATCH v2 1/2] x86, arm64: Move ARCH_WANT_HUGE_PMD_SHARE config in arch/Kconfig
2019-04-25 17:42 UTC (2+ messages)
[PATCH v4 0/4] Miscellaneous kernel command line fixes
2019-04-25 9:59 UTC (8+ messages)
` [PATCH 1/4] RISC-V: Add RISC-V specific arch_match_cpu_phys_id
` [PATCH 2/4] RISC-V: Implement nosmp commandline option
` [PATCH 3/4] RISC-V: Support nr_cpus command line option
` [PATCH 4/4] RISC-V: Fix minor checkpatch issues
[PATCH v4 0/3] Allow accessing CSR using CSR number
2019-04-25 8:17 UTC (8+ messages)
` [PATCH v4 1/3] RISC-V: Use tabs to align macro values in asm/csr.h
` [PATCH v4 2/3] RISC-V: Add interrupt related SCAUSE defines "
` [PATCH v4 3/3] RISC-V: Access CSRs using CSR numbers
[PATCH v5 0/3] Allow accessing CSR using CSR number
2019-04-25 8:15 UTC (4+ messages)
` [PATCH v5 1/3] RISC-V: Use tabs to align macro values in asm/csr.h
` [PATCH v5 2/3] RISC-V: Add interrupt related SCAUSE defines "
` [PATCH v5 3/3] RISC-V: Access CSRs using CSR numbers
[PATCH v3] RISC-V: Implement ASID allocator
2019-04-25 5:55 UTC (7+ messages)
[PATCH v3 0/3] Allow accessing CSR using CSR number
2019-04-25 5:04 UTC (10+ messages)
` [PATCH v3 1/3] RISC-V: Use tabs to align macro values in asm/csr.h
` [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines "
` [PATCH v3 3/3] RISC-V: Access CSRs using CSR numbers
[PATCH v3 2/4] RISC-V: Fix memory reservation in setup_bootmem()
2019-04-24 21:06 UTC (2+ messages)
[PATCH AUTOSEL 4.19 14/52] riscv: fix accessing 8-byte variable from RV32
2019-04-24 14:38 UTC
[PATCH AUTOSEL 5.0 20/66] riscv: fix accessing 8-byte variable from RV32
2019-04-24 14:32 UTC
[PATCH] RISC-V: redefine PTRS_PER_PGD/PTRS_PER_PMD/PTRS_PER_PTE
2019-04-24 8:13 UTC (2+ messages)
[PATCH] RISC-V: redefine PTRS_PER_PGD/PTRS_PER_PMD/PTRS_PER_PTE
2019-04-24 7:59 UTC (2+ messages)
Testing the recent RISC-V DT patchsets
2019-04-23 0:17 UTC
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