From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66609C4332F for ; Fri, 25 Nov 2022 10:47:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=r1/PYuzs5V/n5ikN0k1tJJ3T4tV0dfo+LB3pdSCliVg=; b=bJNA+oxym6ufF7 mpakzyu7y9zepzL+AgzEo6Vi18owIHe7c81R4qHBGQiV4z7JN174/l536r9HIMf/CgmHXudrCuQh1 CcjQl21Y1FuT3EXtDSY3to2DsiMLdViXra8TZfdPi6+EJCfwPNjJ7y3VQNP4hvayzTscQmBddh7wJ 4sd7kyNItnxNFihT0cScn4gwAJGa8OPau3AYCxqc/wqGbhdL9+qLExvmrp0aT/sKg0oSYaSD2dbcE JpcE7htpcSemyx0cFObV6DytlGYd6kExXO/3OptMCX4aq/lvkbcyEegihep7dwEEhD+wwrLMrZDKI SJdvFKzvhlcOoL8h1C+A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oyWEP-00Fejy-Ii; Fri, 25 Nov 2022 10:46:53 +0000 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oyW2S-00FV3F-RG for linux-riscv@lists.infradead.org; Fri, 25 Nov 2022 10:34:34 +0000 Received: by mail-ed1-x529.google.com with SMTP id r26so3717740edc.10 for ; Fri, 25 Nov 2022 02:34:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=ZEpkuQXuvOiX23moyFDnFxgEP2HnqxVQhoNAx7KzG+8=; b=g1drplUkwDolDWizuLqHCWwBVIFGtE+j/n5Lv8jrj37Q8V/JRxyrr1uYt74+0IYE94 tR9HaIOul/fQMbrNbfwHfiXpA7au8Eij7h2sLqEkXI9qrKnCCTuApCnwFgDmw50zkCRS hjnG5nMXWkEqYVxce8AsTogPE20iIRc/PPa+zBx8bwZbZo7m2QbL/blE81mphmiLnMr5 OxTZIneoDveMDLoaiz8fxoK/S41clLqxsOxJ+ztYpT1GVGriwc9MXjW+Q/ls9ZJl1xtq M8PDUfwJ8DLHVyQiBY4J8OC+sM/ffE2bYWJO5HYsVLcenkKxOsjHzu2KfzIMxrKd4AjO jy0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ZEpkuQXuvOiX23moyFDnFxgEP2HnqxVQhoNAx7KzG+8=; b=fOWAsNhsJXgmePrjbGalrYF9L/4YmgaUqV3U4zAJg7TQgPJ/LPt68VTqyIcH6eLh9L krxgUwsHGvKDSCXy4gs18lwu9fjTmuPth5FMwLRtjAUfE8RE1iVt9HJXd4JeofdTZmlK HWra1KTNZG68PxOnX6zG3Z8YF2/VJ3CHR83BY30Cs8Sx97QU75HgjXl+K2KBNB3f+l4e f0y2NfGXNxoJAZlNoeJ/nKSf3lGzkmUTYFhWw6iJA1DpFt2jw00kH9IynY8UP5q2LpDw ukvFwYilrjCLFDlMXnv/EqWUD6FnsYj6m/vB0Fx+rN9qXD/E813/mGDlnwk9XollKJdA OkpQ== X-Gm-Message-State: ANoB5pnq9GEzvK6CoarPPgz53CqD2KeuHrw6CCDC33QUGw5kno3zBOnr exjYdXlglasr1h/CMiW9oLTjDx+10z7mz3dodSw= X-Google-Smtp-Source: AA0mqf5HrlCFHGWi4MUGdrjcLpjKY5UhP4x39kSPBoAH0e6ijoZRD3oKw6heUDDA+5j983c7sUpuxvy2UVbKyB+BAAE= X-Received: by 2002:aa7:d156:0:b0:468:51b0:295 with SMTP id r22-20020aa7d156000000b0046851b00295mr34445349edo.319.1669372471204; Fri, 25 Nov 2022 02:34:31 -0800 (PST) MIME-Version: 1.0 References: <20221124172207.153718-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221124172207.153718-7-prabhakar.mahadev-lad.rj@bp.renesas.com> <70d1bfde-f57f-1741-08d3-23e362793595@linaro.org> In-Reply-To: <70d1bfde-f57f-1741-08d3-23e362793595@linaro.org> From: "Lad, Prabhakar" Date: Fri, 25 Nov 2022 10:34:04 +0000 Message-ID: Subject: Re: [PATCH v4 6/7] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller To: Krzysztof Kozlowski Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Guo Ren , Jisheng Zhang , Atish Patra , Anup Patel , Andrew Jones , Nathan Chancellor , Philipp Tomsich , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Biju Das , Lad Prabhakar X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221125_023432_976973_DFC36DC9 X-CRM114-Status: GOOD ( 32.45 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Krzysztof, Thank you for the review. On Fri, Nov 25, 2022 at 8:16 AM Krzysztof Kozlowski wrote: > > On 24/11/2022 18:22, Prabhakar wrote: > > From: Lad Prabhakar > > > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > > describes the L2 cache block. > > > > Signed-off-by: Lad Prabhakar > > --- > > RFC v3 -> v4 > > * Dropped l2 cache configuration parameters > > * s/larger/large > > * Added minItems/maxItems for andestech,pma-regions > > --- > > .../cache/andestech,ax45mp-cache.yaml | 93 +++++++++++++++++++ > > .../cache/andestech,ax45mp-cache.h | 38 ++++++++ > > 2 files changed, 131 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > > create mode 100644 include/dt-bindings/cache/andestech,ax45mp-cache.h > > > > diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > > new file mode 100644 > > index 000000000000..bf255b177d0a > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > > @@ -0,0 +1,93 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +# Copyright (C) 2022 Renesas Electronics Corp. > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Andestech AX45MP L2 Cache Controller > > + > > +maintainers: > > + - Lad Prabhakar > > + > > +description: > > + A level-2 cache (L2C) is used to improve the system performance by providing > > + a large amount of cache line entries and reasonable access delays. The L2C > > + is shared between cores, and a non-inclusive non-exclusive policy is used. > > + > > +select: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - andestech,ax45mp-cache > > + > > + required: > > + - compatible > > + > > +properties: > > + compatible: > > + items: > > + - const: andestech,ax45mp-cache > > + - const: cache > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + cache-line-size: > > + const: 64 > > + > > + cache-level: > > + const: 2 > > + > > + cache-sets: > > + const: 1024 > > + > > + cache-size: > > + enum: [131072, 262144, 524288, 1048576, 2097152] > > + > > + cache-unified: true > > + > > + next-level-cache: true > > + > > + andestech,pma-regions: > > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > > + minItems: 1 > > + maxItems: 16 > > + items: > > + minItems: 3 > > + maxItems: 3 > > Instead: > items: > items: > - description: Explain > - description: what is > - description: here > Ok, I will do that in the next version. - description: Memory region offset to be set up in the PMA - description: Size of the PMA region - description: Flags indicating how the region should be set up in the PMA. (ETYP[1:0] | MTYP[5:2]) use the macros defined in include/dt-bindings/cache/andestech,ax45mp-cache.h. > > + description: Optional array of memory regions to be set in the PMA. > > + > > +additionalProperties: false > > + > > +required: > > + - compatible > > + - cache-line-size > > + - cache-level > > + - cache-sets > > + - cache-size > > + - cache-unified > > + - interrupts > > + - reg > > Keep the same order as properties appear in the "properties:" > Agreed, will do. > > + > > +examples: > > + - | > > + #include > > + #include > > + > > + cache-controller@2010000 { > > + reg = <0x13400000 0x100000>; > > + compatible = "andestech,ax45mp-cache", "cache"; > > + interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; > > + cache-line-size = <64>; > > + cache-level = <2>; > > + cache-sets = <1024>; > > + cache-size = <262144>; > > + cache-unified; > > + andestech,pma-regions = <0x58000000 0x08000000 > > + (AX45MP_PMACFG_ETYP_NAPOT | AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF)>; > > + }; > > diff --git a/include/dt-bindings/cache/andestech,ax45mp-cache.h b/include/dt-bindings/cache/andestech,ax45mp-cache.h > > new file mode 100644 > > index 000000000000..aa1cad24075d > > --- /dev/null > > +++ b/include/dt-bindings/cache/andestech,ax45mp-cache.h > > @@ -0,0 +1,38 @@ > > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > > +/* > > + * This header provides constants for Andes AX45MP PMA configuration > > + * > > + * Copyright (C) 2022 Renesas Electronics Corp. > > + */ > > + > > +#ifndef __DT_BINDINGS_ANDESTECH_AX45MP_CACHE_H > > +#define __DT_BINDINGS_ANDESTECH_AX45MP_CACHE_H > > + > > +/* OFF: PMA entry is disabled */ > > +#define AX45MP_PMACFG_ETYP_DISABLED 0 > > +/* Naturally aligned power of 2 region */ > > +#define AX45MP_PMACFG_ETYP_NAPOT 3 > > + > > +/* Device, Non-bufferable */ > > +#define AX45MP_PMACFG_MTYP_DEV_NON_BUF (0 << 2) > > +/* Device, bufferable */ > > +#define AX45MP_PMACFG_MTYP_DEV_BUF (1 << 2) > > +/* Memory, Non-cacheable, Non-bufferable */ > > +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_NON_BUF (2 << 2) > > +/* Memory, Non-cacheable, Bufferable */ > > +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF (3 << 2) > > What are all these? They don't look like flags, because 3 = 1 | 2... > they don't look like constants, because we do not use shifts in > constants. Are these some register values? I also do not see the header > being used in the code, so why having a bindings header if it is not > used (DTS is not usage...)? > These are register bit values for the MTYP[5:2] field. The DTS example in the binding doc (above) uses these macros. I haven't included the DTS/I patches with this patchset yet do think I should? Cheers, Prabhakar _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv