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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=tO96KCUrmod4Bc1ngFqk0NF3aHyVouo2a5XyYHy3WtA=; b=IeK7lRamkTNyhuV9/6XKwMk6IyBl/z3+iEmprfJ9e+/NhNMjGWY1SBSZnQJNxLc6zD 60nRlFDLsEEmJ5Ua30JoKUiQAhqq4IKcoeiKZyk5Fw8J8nMmyaY91XDJckU8ocoBxz8Q D3XS5IDSRqXzEK8QOG+oWbio6PWQOl0YJboRGmffbvUxy4d90+XwjTUtD9EaxDk5I/YY 50ogul+uDEFDRAwkLVxYT9eM/aOcP63csIsD9IF2jX1uX2M/JM7Kwv1wgG7ZrTWAnDAd /O5mKN1XtEMLkBwqWQ+dKyAgoPY/HjLs+fCzZjnXCHVSKNPM9REPWcahA0t1YazRGbJl XRvg== X-Gm-Message-State: AJIora/f3tMffpjayd+d2vRPLtWBT6ApAv+8wyKs0jFIeumoKpnZdKDG h4cjIe3OZvsp91b/7TiVXnKpu0mXN6DXMWAOB/Q= X-Google-Smtp-Source: AGRyM1tTw4w511Z1qejEOK9vSuyQPylIYKCBdl8onOcjCJ2A9h7t/jpCh5PWMT+1BJjigzlLpNJe0GLPufh8KC9k13Q= X-Received: by 2002:a25:830f:0:b0:66f:cc60:c740 with SMTP id s15-20020a25830f000000b0066fcc60c740mr17248720ybk.117.1658914549731; Wed, 27 Jul 2022 02:35:49 -0700 (PDT) MIME-Version: 1.0 References: <20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220726180623.1668-5-prabhakar.mahadev-lad.rj@bp.renesas.com> <636e9214-4b36-e9a6-3c6b-b6edb944335e@linaro.org> In-Reply-To: From: "Lad, Prabhakar" Date: Wed, 27 Jul 2022 10:35:22 +0100 Message-ID: Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK To: Biju Das Cc: Krzysztof Kozlowski , Prabhakar Mahadev Lad , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-riscv , LKML X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220727_023550_752423_59A972AF X-CRM114-Status: GOOD ( 26.10 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Biju, On Wed, Jul 27, 2022 at 10:27 AM Biju Das wrote: > > Hi Lad, Prabhakar, > > > Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding > > documentation for Renesas RZ/Five SoC and SMARC EVK > > > > Hi Krzysztof, > > > > Thank you for the review. > > > > On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski > > wrote: > > > > > > On 26/07/2022 20:06, Lad Prabhakar wrote: > > > > Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this > > SoC. > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > > > > --- > > > > .../devicetree/bindings/riscv/renesas.yaml | 49 > > +++++++++++++++++++ > > > > 1 file changed, 49 insertions(+) > > > > create mode 100644 > > > > Documentation/devicetree/bindings/riscv/renesas.yaml > > > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml > > > > b/Documentation/devicetree/bindings/riscv/renesas.yaml > > > > new file mode 100644 > > > > index 000000000000..f72f8aea6a82 > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml > > > > @@ -0,0 +1,49 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > > > +--- > > > > +$id: > > > > > + > > > > +title: Renesas RZ/Five Platform Device Tree Bindings > > > > + > > > > +maintainers: > > > > + - Geert Uytterhoeven > > > > + - Lad Prabhakar > > > > + > > > > +# We want to ignore this schema if the board is SMARC EVK based on > > > > +ARM64 arch > > > > +select: > > > > + not: > > > > + properties: > > > > + compatible: > > > > + contains: > > > > + items: > > > > > > I think you should rather ignore the RiscV SoCs, not specific board. > > > > > You mean to ignore ARM/64 SoCs? > > > > Agreed just the below enum, should do the trick. > > > > - enum: > > - renesas,r9a07g043u11 > > - renesas,r9a07g043u12 > > - renesas,r9a07g044c1 > > - renesas,r9a07g044c2 > > - renesas,r9a07g044l1 > > - renesas,r9a07g044l2 > > - renesas,r9a07g054l1 > > - renesas,r9a07g054l2 > > Why do we need to add renesas,r9a07g044 and renesas,r9a07g054 > in riscv file? These are arm64 only SoC's. > The above needs to be added to avoid dtbs_check/dt_binding_check errors. The above hunk ignores the RISC-V schema if it's an ARM64 SoC. Cheers, Prabhakar > Cheers, > Biju > > > > > > > > > + - const: renesas,smarc-evk > > > > + - enum: > > > > + - renesas,r9a07g043u11 > > > > + - renesas,r9a07g043u12 > > > > + - renesas,r9a07g044c1 > > > > + - renesas,r9a07g044c2 > > > > + - renesas,r9a07g044l1 > > > > + - renesas,r9a07g044l2 > > > > + - renesas,r9a07g054l1 > > > > + - renesas,r9a07g054l2 > > > > + - enum: > > > > + - renesas,r9a07g043 > > > > + - renesas,r9a07g044 > > > > + - renesas,r9a07g054 > > > > > > Did you actually test that it works and properly matches? > > > > > Yes I have run the dtbs_check and dt_binding _check for ARM64 and RISC- > > V. Do you see any cases where it can fail? > > > > Cheers, > > Prabhakar _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv