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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc; bh=JsbjkAc9nKBUwo2BV+lJuV+9wDAaqVtP+AYnXddE06M=; b=4mhi9Sp78dVbWn77GU9P6+Jwy03ZRCFjrefr9vNNN3BjNMyzJSmiNAFLh1O7H9V3pA 3xNc7OJBT6+uZC3akFXV2L0jbb8NDfi2mbV6MbLrQmO2JBmZIOUhumB6EaT//0sS9MPC b+eUEbwkbClUmWVSOeB4wfYqIrnII7/d4geqt5IaCisa8rybAyiHwjZWUfLNAPQpErP/ C9ALI0H88AhrEb+9S/y1h38JWL/BIZKNRO2xg6+2Si5lBL40EhYG5NlZXDGd3yyGDu+h bZW64RIamorTqGitesw1w1dfWH5PHLEJb1LFrwD3Q5/gljJYIEw1wv1pQoTt1Wc62Gus mCNw== X-Gm-Message-State: ACgBeo3qvt210+d4V0/AifC3APPmPStyd749B6F6upxGcad44wiFfaZm QAuWeg4OVI3Z4z5hfKxIb9XQc4vpBPOvNzzZf3w= X-Google-Smtp-Source: AA6agR64CGhHuJItOoEwYlI4Q1qKbjkazebB6e8Fjy2TxN3npFljabqR+ivGNTyMVFhoyPJuhYFBJHKQURNW/HRyAmA= X-Received: by 2002:a25:4689:0:b0:671:6d4f:c974 with SMTP id t131-20020a254689000000b006716d4fc974mr7342816yba.354.1660909359543; Fri, 19 Aug 2022 04:42:39 -0700 (PDT) MIME-Version: 1.0 References: <20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220815151451.23293-6-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: "Lad, Prabhakar" Date: Fri, 19 Aug 2022 12:42:12 +0100 Message-ID: Subject: Re: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC To: Geert Uytterhoeven Cc: Lad Prabhakar , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Conor Dooley , Anup Patel , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-riscv , Linux Kernel Mailing List , Biju Das X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_044242_662668_6F4F01CA X-CRM114-Status: GOOD ( 35.70 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Geert, On Fri, Aug 19, 2022 at 9:05 AM Geert Uytterhoeven wrote: > > Hi Prabhalar, > > On Mon, Aug 15, 2022 at 5:17 PM Lad Prabhakar > wrote: > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > > Single). > > > > Below is the list of IP blocks added in the initial SoC DTSI which can be > > used to boot via initramfs on RZ/Five SMARC EVK: > > - AX45MP CPU > > - CPG > > - PINCTRL > > - PLIC > > - SCIF0 > > - SYSC > > > > Signed-off-by: Lad Prabhakar > > Thanks for your patch! > > > --- /dev/null > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi > > @@ -0,0 +1,121 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +/* > > + * Device Tree Source for the RZ/Five SoC > > My first thought was: > > This should be arch/riscv/boot/dts/renesas/r9a07g043f01.dtsi, > including the common r9a07g043.dtsi, shared by > arch/arm64/boot/dts/renesas/r9a07g043u11.dtsi. > > Then I realized this is harder than it sounds, due: > Indeed, my initial thought after the comments from Conor was we could share the SoC dtsi, but that would be to messey due to PLIC. Cheers, Prabhakar > > + soc: soc { > > + compatible = "simple-bus"; > > + interrupt-parent = <&plic>; > > vs. "interrupt-parent = <&plic>;" for r9a07g043u11, but mostly > due to > > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + scif0: serial@1004b800 { > > + compatible = "renesas,scif-r9a07g043", > > + "renesas,scif-r9a07g044"; > > + reg = <0 0x1004b800 0 0x400>; > > + interrupts = <412 IRQ_TYPE_LEVEL_HIGH>, > > + <414 IRQ_TYPE_LEVEL_HIGH>, > > + <415 IRQ_TYPE_LEVEL_HIGH>, > > + <413 IRQ_TYPE_LEVEL_HIGH>, > > + <416 IRQ_TYPE_LEVEL_HIGH>, > > + <416 IRQ_TYPE_LEVEL_HIGH>; > > vs. "interrupts = ..." on > r9a07g043u11. > Interestingly, the actual hardware interrupt numbers are the same, > but the GIC DT bindings abstracts the offset of 32 by using a second > cell and GIC_SPI. Unfortunately this cannot be handled by some CPP > magic, as dtc does not support arithmetic operations yet. > > I expect this or similar issues to pop up everywhere, when more > RISCV-V SoCs will appear that share the non-CPU parts with ARM SoCs. > > Ignoring this issue, which we probably can solve only later: > Reviewed-by: Geert Uytterhoeven > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv