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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=PSTqWNHag3SUpc3s1sUcZFF6UQb8ezMgBBQvOC4p8IA=; b=q0+EPQMcoxUvokCk1rvv2FyZu7/5mRcuwXoBeEbTDt7UrqUHxJVLYNOW/VkU/snBG3 QkXtHqCWwccgS2f+jrMZ1FnPVa/ZCLuBeUDBX0/bAEYHhpZ9oxU5C1LvZGkZKuxrVWb+ VKBa3i5MVe16V5XSdKtk3gvtoEbgV7fGcmiSggKG7onulJZjoMVzSynq8NTxI7fw84Z0 0AVpSbRYm14njSHTQ1rugxnQPqm3ELitWBpm+WufgRGFwG6c9jZFt+HmZ7zCR3jKV/wT MjkVio0Mi1G5qz5nNo+9O2HCjG/PlShSC2ZlqYJ2mZfSksgt8qNN73xE0JcjPZSQSXlo j5Lw== X-Gm-Message-State: ANoB5pkaI3+2ZZuxzoreRbvJji/GXS3CtPi8EsPbesGiMnlsISd8wuO9 qf61jmeMlx7Rj1LQDK+dYPfvjs0Yy2jCkx0Lbxw= X-Google-Smtp-Source: AA0mqf4/BJoTyjk07S/TT+v6WloICUBFRly4YcWuDlROWrOzgv+5CNKPR50fastJHx25Y7QVIpQuaLjvBbIvs45GkVo= X-Received: by 2002:a17:907:7650:b0:781:e568:294f with SMTP id kj16-20020a170907765000b00781e568294fmr19286209ejc.447.1669400319844; Fri, 25 Nov 2022 10:18:39 -0800 (PST) MIME-Version: 1.0 References: <20221124172207.153718-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221124172207.153718-7-prabhakar.mahadev-lad.rj@bp.renesas.com> <70d1bfde-f57f-1741-08d3-23e362793595@linaro.org> <9b0f8312-2caa-b9f3-edf3-1b720532f559@linaro.org> In-Reply-To: <9b0f8312-2caa-b9f3-edf3-1b720532f559@linaro.org> From: "Lad, Prabhakar" Date: Fri, 25 Nov 2022 18:18:13 +0000 Message-ID: Subject: Re: [PATCH v4 6/7] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller To: Krzysztof Kozlowski Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Guo Ren , Jisheng Zhang , Atish Patra , Anup Patel , Andrew Jones , Nathan Chancellor , Philipp Tomsich , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Biju Das , Lad Prabhakar X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221125_101843_292560_E60F5653 X-CRM114-Status: GOOD ( 18.43 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Krzysztof, On Fri, Nov 25, 2022 at 12:12 PM Krzysztof Kozlowski wrote: > > On 25/11/2022 11:34, Lad, Prabhakar wrote: > >>> +/* Device, Non-bufferable */ > >>> +#define AX45MP_PMACFG_MTYP_DEV_NON_BUF (0 << 2) > >>> +/* Device, bufferable */ > >>> +#define AX45MP_PMACFG_MTYP_DEV_BUF (1 << 2) > >>> +/* Memory, Non-cacheable, Non-bufferable */ > >>> +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_NON_BUF (2 << 2) > >>> +/* Memory, Non-cacheable, Bufferable */ > >>> +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF (3 << 2) > >> > >> What are all these? They don't look like flags, because 3 = 1 | 2... > >> they don't look like constants, because we do not use shifts in > >> constants. Are these some register values? I also do not see the header > >> being used in the code, so why having a bindings header if it is not > >> used (DTS is not usage...)? > >> > > These are register bit values for the MTYP[5:2] field. The DTS example > > in the binding doc (above) uses these macros. I haven't included the > > DTS/I patches with this patchset yet do think I should? > > Then why storing it as bindings? Bindings headers describe the interface > implemented by drivers and used by DTS, but this is not implemented by > drivers. > I got your point. I'll make use of the header in the driver for the next version and fix your previously pointed comments. Cheers, Prabhakar _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv