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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Lp2UjJeoZNtF3jPddaeCcZ2oTGYQdnwK+wO4WeAagn8=; b=me4mdykxFqW9lu18CugvhEcg+xP/Y3aSOYnlneMGmgn2gqaXs5x/OWHzEza3CpBDZs MDnSQvLVMO/auHCJL1sJRLSJ+stiws1ktUKl7KgAjLwLbHsTC8pZnQ0wqdPe6oVNJDDS gF6i05HMNRELog3Tz6KVqsZ2O9HqGhb4Vygo+reotRffUZ82s37IfjqOAtBkOL6Vb/Ce AJB6hDFFS22avrbyGvb0nDRmm+s08QOmjpQgq9RK5oejdsvW4dJoTVE1frKvwIOGZ3Bs 9oFJapO7YrUXHhxBe5pnauOuuLuv0vBAXTlKBaYsXha77psMF+l2sj7LDSXEtjJYmfQV 4YXg== X-Gm-Message-State: AJIora97QHHB3Zo8Dcp1K9nLX+A+IwlIZdP2qOqW8fq1huBxl5q3a9w2 TGIaS+TCsSdZLQbVLRxlOCBFqhNjdjdKIo7EtYY= X-Google-Smtp-Source: AGRyM1ueFJysPUexyidBDBCQ2Ajm5GpI2JfoVj8pVsuoL+AzQRgL3tl0GMPhkouwXL5dOZX4XHhkjaJbr0lJsLccxPg= X-Received: by 2002:a05:6902:20a:b0:670:c563:9180 with SMTP id j10-20020a056902020a00b00670c5639180mr16432213ybs.401.1658912446846; Wed, 27 Jul 2022 02:00:46 -0700 (PDT) MIME-Version: 1.0 References: <20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220726180623.1668-2-prabhakar.mahadev-lad.rj@bp.renesas.com> <952a85ec-d1e9-7c14-6404-bc087723252f@linaro.org> In-Reply-To: <952a85ec-d1e9-7c14-6404-bc087723252f@linaro.org> From: "Lad, Prabhakar" Date: Wed, 27 Jul 2022 10:00:19 +0100 Message-ID: Subject: Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch To: Krzysztof Kozlowski Cc: Lad Prabhakar , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-riscv , LKML , Biju Das X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220727_020051_095256_1BF02EA5 X-CRM114-Status: GOOD ( 14.26 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Krzysztof, On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski wrote: > > On 26/07/2022 20:06, Lad Prabhakar wrote: > > Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK > > (RISC-V arch). > > > > Signed-off-by: Lad Prabhakar > > --- > > Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++ > > 1 file changed, 9 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml > > index ff80152f092f..f646df1a23af 100644 > > --- a/Documentation/devicetree/bindings/arm/renesas.yaml > > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml > > @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings > > maintainers: > > - Geert Uytterhoeven > > > > +# We want to ignore this schema if the board is of RISC-V arch > > +select: > > + not: > > + properties: > > + compatible: > > + contains: > > + items: > > + - const: renesas,r9a07g043f01 > > Second issue - why not renesas,r9a07g043? > We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V. RZ/G2UL ARM64: Type-1 Part Number: R9A07G043U11GBG#BC0 Type-2 Part Number: R9A07G043U12GBG#BC0 RZ/Five RISCV: 13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0 So to differentiate in ARM schema I am using renesas,r9a07g043f01. Cheers, Prabhakar _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv