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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=0O5y3zxJLjO+OFcgaKEEvfFc20FWAOhAiAEXszX5msk=; b=WMmsQbBkiUdqlStfFihK/NfM2e4+Q8s/xpmplnDprecLGfC8NQBLIIdul5JYslZXJW oC7BECbPONzlvdTZvFIFVzU8XHl3BlFUcOgBFMo2XzyoWqAtMVoqNBKAK2WiYXXw0njX GYZJ6OuFbu43s189CqPzt6UbjWgoSZLPV3XkXJZlQTDudu1Z52BaJLjKgdef47C4vJAW B23cbgpXUuNQrWYLQ/qFOvnEBkXLbeL+tLfsRqRMPqTgPjfNq4hJR+9fSLtP9Dnfz/Yo az/p0pW6xjqnT7L5up0m+e77gJVxhyFKpRNiCFkLfHGIVbXp4zSmtMWoyX6t9HZBEQK7 ngIg== X-Gm-Message-State: APjAAAXFykNowQBnzK6QXDzEKbJAb5sop33B7l0XmXTL9wDq/FNlibIl aTdt6QdaJSfla9pPmO2ucZmtsYaUkwi3QbMdLZc= X-Google-Smtp-Source: APXvYqyU0iW+NSklLJf3qHZtRLKPHQxuDtnO3IWUd1+SsBVtZYgctk9VnfK45znYVuqr6WdQ3tVVp0jlNS88Khwb+FQ= X-Received: by 2002:ac2:5337:: with SMTP id f23mr7428221lfh.15.1559347790765; Fri, 31 May 2019 17:09:50 -0700 (PDT) MIME-Version: 1.0 References: <20190530222922.4269-1-luke.r.nels@gmail.com> In-Reply-To: From: Alexei Starovoitov Date: Fri, 31 May 2019 17:09:39 -0700 Message-ID: Subject: Re: [PATCH bpf v2] bpf, riscv: clear high 32 bits for ALU32 add/sub/neg/lsh/rsh/arsh To: Palmer Dabbelt X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190531_170953_279631_196D56E5 X-CRM114-Status: GOOD ( 11.54 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Song Liu , aou@eecs.berkeley.edu, bpf , Daniel Borkmann , luke.r.nels@gmail.com, =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Alexei Starovoitov , LKML , Network Development , Yonghong Song , linux-riscv@lists.infradead.org, Martin KaFai Lau , Xi Wang Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, May 31, 2019 at 1:40 PM Palmer Dabbelt wrote: > > On Thu, 30 May 2019 15:29:22 PDT (-0700), luke.r.nels@gmail.com wrote: > > In BPF, 32-bit ALU operations should zero-extend their results into > > the 64-bit registers. > > > > The current BPF JIT on RISC-V emits incorrect instructions that perform > > sign extension only (e.g., addw, subw) on 32-bit add, sub, lsh, rsh, > > arsh, and neg. This behavior diverges from the interpreter and JITs > > for other architectures. > > > > This patch fixes the bugs by performing zero extension on the destination > > register of 32-bit ALU operations. > > > > Fixes: 2353ecc6f91f ("bpf, riscv: add BPF JIT for RV64G") > > Cc: Xi Wang > > Signed-off-by: Luke Nelson > > Reviewed-by: Palmer Dabbelt > > Thanks! I'm assuming this is going in through a BPF tree and not the RISC-V > tree, but LMK if that's not the case. Applied to bpf tree. Thanks _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv