From: anup@brainfault.org (Anup Patel)
To: linux-riscv@lists.infradead.org
Subject: [RFC 0/2] RISC-V: A proposal to add vendor-specific code
Date: Wed, 31 Oct 2018 16:46:10 +0530 [thread overview]
Message-ID: <CAAhSdy0Y_jdc=2Lf8epof_+7HigCfhDxMNe8EF0fHfncqhs-zA@mail.gmail.com> (raw)
In-Reply-To: <1540982130-28248-1-git-send-email-vincentc@andestech.com>
On Wed, Oct 31, 2018 at 4:06 PM Vincent Chen <vincentc@andestech.com> wrote:
>
> RISC-V permits each vendor to develop respective extension ISA based
> on RISC-V standard ISA. This means that these vendor-specific features
> may be compatible to their compiler and CPU. Therefore, each vendor may
> be considered a sub-architecture of RISC-V. Currently, vendors do not
> have the appropriate examples to add these specific features to the
> kernel. In this RFC set, we propose an infrastructure that vendor can
> easily hook their specific features into kernel. The first commit is
> the main body of this infrastructure. In the second commit, we provide
> a solution that allows dma_map_ops() to work without cache coherent
> agent support. Cache coherent agent is unsupported for low-end CPUs in
> the AndeStar RISC-V series. In order for Linux to run on these CPUs, we
> need this solution to overcome the limitation of cache coherent agent
> support. Hence, it also can be used as an example for the first commit.
>
> I am glad to discuss any ideas, so if you have any idea, please give
> me some feedback.
>
I agree that we need a place for vendor-specific ISA extensions and
having vendor-specific directories is also good.
What I don't support is the approach of having compile time selection
of vendor-specific ISA extension.
We should have runtime probing for compatible vendor-specific ISA
extension. Also, it should be possible to link multiple vendor-specific
SA extensions to same kernel image. This way we can have a single
kernel image (along with various vendor-specific ISA extensions) which
works on variety of targets/hosts.
As an example or runtime probing you can look at how IRQCHIP or
CLOCKSOURCE drivers are probed. The vendor-specific ISA extension
hooks should called in similar fashion.
Regards,
Anup
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup@brainfault.org>
To: vincentc@andestech.com
Cc: Albert Ou <aou@eecs.berkeley.edu>, Arnd Bergmann <arnd@arndb.de>,
alankao@andestech.com, greentime@andestech.com,
Palmer Dabbelt <palmer@sifive.com>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>, Zong Li <zong@andestech.com>,
linux-riscv@lists.infradead.org, deanbo422@gmail.com
Subject: Re: [RFC 0/2] RISC-V: A proposal to add vendor-specific code
Date: Wed, 31 Oct 2018 16:46:10 +0530 [thread overview]
Message-ID: <CAAhSdy0Y_jdc=2Lf8epof_+7HigCfhDxMNe8EF0fHfncqhs-zA@mail.gmail.com> (raw)
Message-ID: <20181031111610.x4sCcNY23xfQB_TPjZWW6D4ii_H_ShPFRHjSV0t5y3s@z> (raw)
In-Reply-To: <1540982130-28248-1-git-send-email-vincentc@andestech.com>
On Wed, Oct 31, 2018 at 4:06 PM Vincent Chen <vincentc@andestech.com> wrote:
>
> RISC-V permits each vendor to develop respective extension ISA based
> on RISC-V standard ISA. This means that these vendor-specific features
> may be compatible to their compiler and CPU. Therefore, each vendor may
> be considered a sub-architecture of RISC-V. Currently, vendors do not
> have the appropriate examples to add these specific features to the
> kernel. In this RFC set, we propose an infrastructure that vendor can
> easily hook their specific features into kernel. The first commit is
> the main body of this infrastructure. In the second commit, we provide
> a solution that allows dma_map_ops() to work without cache coherent
> agent support. Cache coherent agent is unsupported for low-end CPUs in
> the AndeStar RISC-V series. In order for Linux to run on these CPUs, we
> need this solution to overcome the limitation of cache coherent agent
> support. Hence, it also can be used as an example for the first commit.
>
> I am glad to discuss any ideas, so if you have any idea, please give
> me some feedback.
>
I agree that we need a place for vendor-specific ISA extensions and
having vendor-specific directories is also good.
What I don't support is the approach of having compile time selection
of vendor-specific ISA extension.
We should have runtime probing for compatible vendor-specific ISA
extension. Also, it should be possible to link multiple vendor-specific
SA extensions to same kernel image. This way we can have a single
kernel image (along with various vendor-specific ISA extensions) which
works on variety of targets/hosts.
As an example or runtime probing you can look at how IRQCHIP or
CLOCKSOURCE drivers are probed. The vendor-specific ISA extension
hooks should called in similar fashion.
Regards,
Anup
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next prev parent reply other threads:[~2018-10-31 11:16 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-31 10:35 [RFC 0/2] RISC-V: A proposal to add vendor-specific code Vincent Chen
2018-10-31 10:35 ` Vincent Chen
2018-10-31 10:35 ` [RFC 1/2] RISC-V: An infrastructure " Vincent Chen
2018-10-31 10:35 ` Vincent Chen
2018-10-31 10:35 ` [RFC 2/2] RISC-V: make dma_map_ops work without cache coherent agent Vincent Chen
2018-10-31 10:35 ` Vincent Chen
2018-10-31 11:16 ` Anup Patel [this message]
2018-10-31 11:16 ` [RFC 0/2] RISC-V: A proposal to add vendor-specific code Anup Patel
2018-10-31 11:45 ` Arnd Bergmann
2018-10-31 11:45 ` Arnd Bergmann
2018-10-31 14:17 ` Christoph Hellwig
2018-10-31 14:17 ` Christoph Hellwig
2018-11-01 0:55 ` Alan Kao
2018-11-01 0:55 ` Alan Kao
2018-11-01 17:50 ` Palmer Dabbelt
2018-11-01 17:50 ` Palmer Dabbelt
2018-11-02 0:41 ` Alan Kao
2018-11-02 0:41 ` Alan Kao
2018-10-31 17:27 ` Palmer Dabbelt
2018-10-31 17:27 ` Palmer Dabbelt
2018-10-31 19:17 ` Olof Johansson
2018-10-31 19:17 ` Olof Johansson
2018-11-01 17:48 ` Karsten Merker
2018-11-05 6:58 ` Vincent Chen
2018-11-05 6:58 ` Vincent Chen
2018-11-05 7:05 ` Christoph Hellwig
2018-11-05 7:05 ` Christoph Hellwig
2018-11-05 8:52 ` Arnd Bergmann
2018-11-05 8:52 ` Arnd Bergmann
2018-11-05 9:08 ` Christoph Hellwig
2018-11-05 9:08 ` Christoph Hellwig
2018-11-05 13:51 ` Arnd Bergmann
2018-11-05 13:51 ` Arnd Bergmann
2018-11-06 6:59 ` Christoph Hellwig
2018-11-06 6:59 ` Christoph Hellwig
2018-11-06 23:45 ` Palmer Dabbelt
2018-11-06 23:45 ` Palmer Dabbelt
2018-11-07 9:51 ` Arnd Bergmann
2018-11-07 9:51 ` Arnd Bergmann
2018-11-06 23:45 ` Palmer Dabbelt
2018-11-06 23:45 ` Palmer Dabbelt
2018-11-08 2:43 ` Vincent Chen
2018-11-08 2:43 ` Vincent Chen
2018-11-05 19:39 ` Nick Kossifidis
2018-11-05 19:39 ` Nick Kossifidis
2018-11-06 6:56 ` Christoph Hellwig
2018-11-06 6:56 ` Christoph Hellwig
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