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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Mar 27, 2019 at 6:11 AM Gary Guo wrote: > > From: Gary Guo > > This patch implements IPI-based remote TLB shootdown, which is useful > at this stage for testing because BBL/OpenSBI ignores operands of > sbi_remote_sfence_vma_asid and always perform a global TLB flush. > The SBI-based remote TLB shootdown can still be opt-in using boot > cmdline "tlbi_method=sbi". > > Signed-off-by: Gary Guo > Tested-by: Atish Patra > --- > .../admin-guide/kernel-parameters.txt | 5 + > arch/riscv/mm/tlbflush.c | 99 +++++++++++++++++-- > 2 files changed, 98 insertions(+), 6 deletions(-) > > diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt > index 7a60edef09d2..afd34fa1db91 100644 > --- a/Documentation/admin-guide/kernel-parameters.txt > +++ b/Documentation/admin-guide/kernel-parameters.txt > @@ -4552,6 +4552,11 @@ > flushed. > See arch/riscv/mm/tlbflush.c > > + tlbi_method= [RV] > + Format: { "sbi", "ipi" } > + Default: "ipi" > + Specify the method used to perform remote TLB shootdown. > + > tmem [KNL,XEN] > Enable the Transcendent memory driver if built-in. > > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c > index 33083f48a936..ceee76f14a0a 100644 > --- a/arch/riscv/mm/tlbflush.c > +++ b/arch/riscv/mm/tlbflush.c > @@ -72,19 +72,106 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) > > #ifdef CONFIG_SMP > > +/* > + * SBI has interfaces for remote TLB shootdown. If there is no hardware > + * remote TLB shootdown support, SBI perform IPIs itself instead. Some SBI > + * implementations may also ignore ASID and address ranges provided and do a > + * full TLB flush instead. In these cases we might want to do IPIs ourselves. > + * > + * This parameter allows the approach (IPI/SBI) to be specified using boot > + * cmdline. > + */ > +static bool tlbi_ipi = true; > + > +static int __init setup_tlbi_method(char *str) > +{ > + if (strcmp(str, "ipi") == 0) > + tlbi_ipi = true; > + else if (strcmp(str, "sbi") == 0) > + tlbi_ipi = false; > + else > + return -EINVAL; > + > + return 0; > +} > +early_param("tlbi_method", setup_tlbi_method); > + > + > +struct tlbi { > + unsigned long start; > + unsigned long size; > + unsigned long asid; > +}; > + > +static void ipi_remote_sfence_vma(void *info) > +{ > + struct tlbi *data = info; > + unsigned long start = data->start; > + unsigned long size = data->size; > + unsigned long i; > + > + if (size == SFENCE_VMA_FLUSH_ALL) { > + local_flush_tlb_all(); > + } No brace required here. > + > + for (i = 0; i < size; i += PAGE_SIZE) { > + __asm__ __volatile__ ("sfence.vma %0" > + : : "r" (start + i) > + : "memory"); > + } No brace required here as well. > +} > + > +static void ipi_remote_sfence_vma_asid(void *info) > +{ > + struct tlbi *data = info; > + unsigned long asid = data->asid; > + unsigned long start = data->start; > + unsigned long size = data->size; > + unsigned long i; > + > + if (size == SFENCE_VMA_FLUSH_ALL) { > + __asm__ __volatile__ ("sfence.vma x0, %0" > + : : "r" (asid) > + : "memory"); > + return; > + } > + > + for (i = 0; i < size; i += PAGE_SIZE) { > + __asm__ __volatile__ ("sfence.vma %0, %1" > + : : "r" (start + i), "r" (asid) > + : "memory"); > + } No brace required here as well. > +} > + > static void remote_sfence_vma(unsigned long start, unsigned long size) > { > - sbi_remote_sfence_vma(NULL, start, size); > + if (tlbi_ipi) { > + struct tlbi info = { > + .start = start, > + .size = size, > + }; > + on_each_cpu(ipi_remote_sfence_vma, &info, 1); > + } else > + sbi_remote_sfence_vma(NULL, start, size); > } > > static void remote_sfence_vma_asid(cpumask_t *mask, unsigned long start, > unsigned long size, unsigned long asid) > { > - cpumask_t hmask; > - > - cpumask_clear(&hmask); > - riscv_cpuid_to_hartid_mask(mask, &hmask); > - sbi_remote_sfence_vma_asid(hmask.bits, start, size, asid); > + if (tlbi_ipi) { > + struct tlbi info = { > + .start = start, > + .size = size, > + .asid = asid, > + }; > + on_each_cpu_mask(mask, ipi_remote_sfence_vma_asid, &info, 1); > + } else { > + cpumask_t hmask; > + > + cpumask_clear(&hmask); > + riscv_cpuid_to_hartid_mask(mask, &hmask); > + sbi_remote_sfence_vma_asid(hmask.bits, start, size, asid); > + } > } > > > -- > 2.17.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv Regards, Anup _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv