From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EF58C04EBF for ; Mon, 23 Sep 2019 13:10:03 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0D01C20835 for ; Mon, 23 Sep 2019 13:10:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="T+u3nScQ"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="BX0d9fUZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0D01C20835 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=87F1C4QgDvCpJEANg55M4aoewxFrCUBW5N+Bj6rUY4Q=; b=T+u3nScQepw5c/ ChndP+ADfr8erFfN/q+xotD16UX7mVV8Potg6Vcjb8QYgyqBJ0swwA1v61kzOX4EFilTeUELGlVsz RLT3HKZrP4H4IbHsX+Qgjm1HVXVgGQy5ETBmW/MtvEFkfF8QQy0x5GIccJctCb2L/UB5ESaZeqJk5 sqjuqmjH/uze5eV3q2Kur9eUiFvvehx8tyElqEtCM9JVdJATl0NEbJ/3/HW752FLGmPWHNKGQl6ma B6nlUWemqZz76bm2YJjdKrd/iHuihT8oU7FlZZILDBcYQN/H2nk9jxmUM5Szidz8FIhd/Q9zDkqw0 xCyzn7CzxqjqaMTFJHwg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iCO6M-0006Sc-L6; Mon, 23 Sep 2019 13:10:02 +0000 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iCO6K-0006EW-RH for linux-riscv@lists.infradead.org; Mon, 23 Sep 2019 13:10:02 +0000 Received: by mail-wm1-x344.google.com with SMTP id p7so9893638wmp.4 for ; Mon, 23 Sep 2019 06:09:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=POQzEF32pJw+JcJGYwatIQLE1EclVL51HgsgtLA7Qmw=; b=BX0d9fUZ89UyQbARi+EIiuQz7/skB03FkmvzPaRZR3ZECUUjvMHRyuchQCs+a9LAea 2G+PIK23wzO+ITkoV9HFRLsgbyKRheMT1vim2zYSLgpWoWWc768/w/OGIxA96QWxNPvq SJEKRVfFuMmfOJ4unliQJ5+TqqUvYFiIxrGMrgtRcVF3bmfjsXCvhjEXGeLH1u++HYAe qbVfRinf3ErfTk1H3EIgzb+9pP38kcbHr+3YQCq6Js11GuGfHHbjTYGjPwlL63q3Y4/U SKvhbtyKQWs8UXSHYGStv9Jl55kLNR8viy0MdL8sHCwy11YhD12ccd5rFMgoUxtK2ykE sItA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=POQzEF32pJw+JcJGYwatIQLE1EclVL51HgsgtLA7Qmw=; b=MyYde0FuFzTZcxUwnlcUp4YhiyGgqBd3eBXVBUE2wMpEmeLgUntXuk4pruVXiFIGne QObo7yFH+dN13NOZiyShpZJWLqssthaujtl+2LPXVi/PAKOZi+6dhJXxKMnz+6M0/0B/ 18Tkx4yGYcrfXCWQfYMnDZcKPWUZbP00dkmS7KGW/ch1zJsm5o+CrWNUxvx2YxAwOl+Y g1iZAfdCgvIxRsU8X4aWXxv7KFWQRG142DIUd3d6ESWve9xRAFpXuv8/1Rc/iCaHyMl+ qFiD6dYeG8cQaeyPmPeR609bHZz7sbjZwtiKlrcfPSOSRnAC30RpXL3vMju8nsKo3Hfo QK8A== X-Gm-Message-State: APjAAAXzXB0hUeTEsOdTY7jshn5fIAZJMNIRA5yQSfpvk6m6Hjt7lIO5 Df6PjLGCd3HiBBmKM95LlT60Vbg+5ZfyN9l5U5fxig== X-Google-Smtp-Source: APXvYqxmSBlwd2lVkFWxE9RTK2LVohXpZcBHo1U2r2gpRoUOnN9IsM4d5615+AEz4vMLdLGhar/FgZSJ+9bVZz2tU3M= X-Received: by 2002:a7b:c84f:: with SMTP id c15mr12094316wml.52.1569244194712; Mon, 23 Sep 2019 06:09:54 -0700 (PDT) MIME-Version: 1.0 References: <20190904161245.111924-1-anup.patel@wdc.com> <20190904161245.111924-12-anup.patel@wdc.com> <8c44ac8a-3fdc-b9dd-1815-06e86cb73047@redhat.com> In-Reply-To: <8c44ac8a-3fdc-b9dd-1815-06e86cb73047@redhat.com> From: Anup Patel Date: Mon, 23 Sep 2019 18:39:43 +0530 Message-ID: Subject: Re: [PATCH v7 10/21] RISC-V: KVM: Handle MMIO exits for VCPU To: Paolo Bonzini X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190923_061000_887652_7C966634 X-CRM114-Status: GOOD ( 13.95 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Palmer Dabbelt , Daniel Lezcano , "kvm@vger.kernel.org" , Radim K , Anup Patel , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alexander Graf , Paul Walmsley , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Sep 23, 2019 at 4:42 PM Paolo Bonzini wrote: > > On 04/09/19 18:15, Anup Patel wrote: > > + unsigned long guest_sstatus = > > + vcpu->arch.guest_context.sstatus | SR_MXR; > > + unsigned long guest_hstatus = > > + vcpu->arch.guest_context.hstatus | HSTATUS_SPRV; > > + unsigned long guest_vsstatus, old_stvec, tmp; > > + > > + guest_sstatus = csr_swap(CSR_SSTATUS, guest_sstatus); > > + old_stvec = csr_swap(CSR_STVEC, (ulong)&__kvm_riscv_unpriv_trap); > > + > > + if (read_insn) { > > + guest_vsstatus = csr_read_set(CSR_VSSTATUS, SR_MXR); > > Is this needed? IIUC SSTATUS.MXR encompasses a wider set of permissions: > > The HS-level MXR bit makes any executable page readable. {\tt > vsstatus}.MXR makes readable those pages marked executable at the VS > translation level, but only if readable at the guest-physical > translation level. > > So it should be enough to set SSTATUS.MXR=1 I think. But you also > shouldn't set SSTATUS.MXR=1 in the !read_insn case. I was being overly cautious here. Initially, I thought SSTATUS.MXR applies only to Stage2 and VSSTATUS.MXR applies only to Stage1. I agree with you. The HS-mode should only need to set SSTATUS.MXR. > > Also, you can drop the irq save/restore (which is already a save/restore > of SSTATUS) since you already write 0 to SSTATUS.SIE in your csr_swap. > Perhaps add a BUG_ON(guest_sstatus & SR_SIE) before the csr_swap? I had already dropped irq save/restore in v7 series and having BUG_ON() on guest_sstatus here would be better. > > > + asm volatile ("\n" > > + "csrrw %[hstatus], " STR(CSR_HSTATUS) ", %[hstatus]\n" > > + "li %[tilen], 4\n" > > + "li %[tscause], 0\n" > > + "lhu %[val], (%[addr])\n" > > + "andi %[tmp], %[val], 3\n" > > + "addi %[tmp], %[tmp], -3\n" > > + "bne %[tmp], zero, 2f\n" > > + "lhu %[tmp], 2(%[addr])\n" > > + "sll %[tmp], %[tmp], 16\n" > > + "add %[val], %[val], %[tmp]\n" > > + "2: csrw " STR(CSR_HSTATUS) ", %[hstatus]" > > + : [hstatus] "+&r"(guest_hstatus), [val] "=&r" (val), > > + [tmp] "=&r" (tmp), [tilen] "+&r" (tilen), > > + [tscause] "+&r" (tscause) > > + : [addr] "r" (addr)); > > + csr_write(CSR_VSSTATUS, guest_vsstatus); > > > > > +#ifndef CONFIG_RISCV_ISA_C > > + "li %[tilen], 4\n" > > +#else > > + "li %[tilen], 2\n" > > +#endif > > Can you use an assembler directive to force using a non-compressed > format for ld and lw? This would get rid of tilen, which is costing 6 > bytes (if I did the RVC math right) in order to save two. :) I tried looking for it but could not find any assembler directive to selectively turn-off instruction compression. > > Paolo > > > + "li %[tscause], 0\n" > > +#ifdef CONFIG_64BIT > > + "ld %[val], (%[addr])\n" > > +#else > > + "lw %[val], (%[addr])\n" > > +#endif Regards, Anup _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv