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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=PFrPzzwmpyAD/udwXE359rvjJD5ZEgk+K9aOBrdRGe4=; b=CuSKvUEDSKzhjw9dkQzFSb42g1p2pzBpYN6zEEJYIYpjsoD+bGHc4hhwNuM9yG+1UG uDRKcNKRH3ioIzZPMMgG7Ub4y6aTgqx/owFfoEglROQdf7CRebJ4Vxk0VOsYeUzuxULp +uhcMupa6op9Mmd7OgABTHxYk4jAnf7LPIWLtBnhF8Llq/FdAMiQnCai+bdgja/MAqwi U6eMCQ2ffZmrl/tKYSb6upgN4SBCLOZtz96AgWanznJbSjKrqZCE5m6L33lueLstfYae v6gLehmCneKgUBbut187faF+yNLROL4nHfQPoGWJPXXxPKku8kUenCZ+r6LLqt6pWOrh TBSA== X-Gm-Message-State: APjAAAWQeHTNYYtqsPw67CROuN+yT0iGH8ZmJI1+hhxfUS/ycr/STX4P uQ1++yxixjSroIJUThoahOebQCs7PRglWCd7YvH2EA== X-Google-Smtp-Source: APXvYqxSVPM8kfU6Iae8q2VWGU/sIXjjlqOBO7h73TYwMqPDl2u3Q1WJfEz4BPOyClmmzeP2Q3AidC1kme6QlYOAk0c= X-Received: by 2002:a05:600c:285:: with SMTP id 5mr6773557wmk.120.1582082929545; Tue, 18 Feb 2020 19:28:49 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Anup Patel Date: Wed, 19 Feb 2020 08:58:38 +0530 Message-ID: Subject: Re: [PATCH] RISC-V: Don't enable all interrupts in trap_init() To: Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200218_192853_053418_77764178 X-CRM114-Status: GOOD ( 21.90 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Atish Patra , Anup Patel , "linux-kernel@vger.kernel.org List" , stable@vger.kernel.org, Atish Patra , Alistair Francis , Paul Walmsley , linux-riscv , Christoph Hellwig Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Feb 19, 2020 at 12:06 AM Palmer Dabbelt wrote: > > On Sun, 02 Feb 2020 03:48:18 PST (-0800), atishp@atishpatra.org wrote: > > On Sun, Feb 2, 2020 at 3:06 AM Anup Patel wrote: > >> > >> Historically, we have been enabling all interrupts for each > >> HART in trap_init(). Ideally, we should only enable M-mode > >> interrupts for M-mode kernel and S-mode interrupts for S-mode > >> kernel in trap_init(). > >> > >> Currently, we get suprious S-mode interrupts on Kendryte K210 > >> board running M-mode NO-MMU kernel because we are enabling all > >> interrupts in trap_init(). To fix this, we only enable software > >> and external interrupt in trap_init(). In future, trap_init() > >> will only enable software interrupt and PLIC driver will enable > >> external interrupt using CPU notifiers. > > I think we should add a proper interrupt controller driver for the per-hart > interrupt controllers, as doing this within the other drivers is ugly -- for > example, there's no reason an MMIO timer or interrupt controller driver should > be toggling these bits. I have always been in support of having per-hart interrupt controller driver. I will rebase my RISC-V INTC driver upon latest kernel and send it again. Of course, now the situation has changed the RISC-V INTC driver will have to consider NOMMU kernel as well. The last version of RISC-V INTC driver can be found in riscv_intc_v2 branch of https://github.com/avpatel/linux.git > > >> Cc: stable@vger.kernel.org > >> Fixes: 76d2a0493a17 ("RISC-V: Init and Halt Code) > > I'd argue this actually fixes the M-mode stuff, since that's the first place > this issue shows up. I've queued this with > > Fixes: a4c3733d32a7 ("riscv: abstract out CSR names for supervisor vs machine mode") > > instead, as that's the first commit that will actually write to MIE and > therefor the first commit that will actually exhibit bad behavior. It also has > the advantage of making the patch apply on older trees, which should make life > easier for the stable folks. Sure, no problem. > > >> Signed-off-by: Anup Patel > >> --- > >> arch/riscv/kernel/traps.c | 4 ++-- > >> 1 file changed, 2 insertions(+), 2 deletions(-) > >> > >> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c > >> index f4cad5163bf2..ffb3d94bf0cc 100644 > >> --- a/arch/riscv/kernel/traps.c > >> +++ b/arch/riscv/kernel/traps.c > >> @@ -156,6 +156,6 @@ void __init trap_init(void) > >> csr_write(CSR_SCRATCH, 0); > >> /* Set the exception vector address */ > >> csr_write(CSR_TVEC, &handle_exception); > >> - /* Enable all interrupts */ > >> - csr_write(CSR_IE, -1); > >> + /* Enable interrupts */ > >> + csr_write(CSR_IE, IE_SIE | IE_EIE); > >> } > >> -- > >> 2.17.1 > >> > >> > > > > Looks good. > > Reviewed-by: Atish Patra > > Tested-by: Palmer Dabbelt [QMEU virt machine with SMP] > Reviewed-by: Palmer Dabbelt > > I consider this a bugfix, so I'm targeting it for RCs. It's on fixes and > should go up this week. > > Thanks! Thanks, Anup