* [PATCH v5 1/4] RISC-V: Mark existing SBI as 0.1 SBI.
2019-11-26 19:04 [PATCH v5 0/4] Add support for SBI v0.2 Atish Patra
@ 2019-11-26 19:05 ` Atish Patra
2019-12-02 23:59 ` Palmer Dabbelt
2019-11-26 19:05 ` [PATCH v5 2/4] RISC-V: Add basic support for SBI v0.2 Atish Patra
` (3 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: Atish Patra @ 2019-11-26 19:05 UTC (permalink / raw)
To: linux-kernel
Cc: Albert Ou, Alexios Zavras, Anup Patel, Mike Rapoport,
Atish Patra, Palmer Dabbelt, Paul Walmsley, linux-riscv,
Thomas Gleixner, Mao Han
As per the new SBI specification, current SBI implementation version
is defined as 0.1 and will be removed/replaced in future. Each of the
function call in 0.1 is defined as a separate extension which makes
easier to replace them one at a time.
Rename existing implementation to reflect that. This patch is just
a preparatory patch for SBI v0.2 and doesn't introduce any functional
changes.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
arch/riscv/include/asm/sbi.h | 43 +++++++++++++++++++-----------------
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 2570c1e683d3..96aaee270ded 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -9,17 +9,17 @@
#include <linux/types.h>
#ifdef CONFIG_RISCV_SBI
-#define SBI_SET_TIMER 0
-#define SBI_CONSOLE_PUTCHAR 1
-#define SBI_CONSOLE_GETCHAR 2
-#define SBI_CLEAR_IPI 3
-#define SBI_SEND_IPI 4
-#define SBI_REMOTE_FENCE_I 5
-#define SBI_REMOTE_SFENCE_VMA 6
-#define SBI_REMOTE_SFENCE_VMA_ASID 7
-#define SBI_SHUTDOWN 8
+#define SBI_EXT_0_1_SET_TIMER 0x0
+#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
+#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
+#define SBI_EXT_0_1_CLEAR_IPI 0x3
+#define SBI_EXT_0_1_SEND_IPI 0x4
+#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
+#define SBI_EXT_0_1_SHUTDOWN 0x8
-#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \
+#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \
register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
@@ -43,48 +43,50 @@
static inline void sbi_console_putchar(int ch)
{
- SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch);
+ SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch);
}
static inline int sbi_console_getchar(void)
{
- return SBI_CALL_0(SBI_CONSOLE_GETCHAR);
+ return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR);
}
static inline void sbi_set_timer(uint64_t stime_value)
{
#if __riscv_xlen == 32
- SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32);
+ SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value,
+ stime_value >> 32);
#else
- SBI_CALL_1(SBI_SET_TIMER, stime_value);
+ SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value);
#endif
}
static inline void sbi_shutdown(void)
{
- SBI_CALL_0(SBI_SHUTDOWN);
+ SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN);
}
static inline void sbi_clear_ipi(void)
{
- SBI_CALL_0(SBI_CLEAR_IPI);
+ SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI);
}
static inline void sbi_send_ipi(const unsigned long *hart_mask)
{
- SBI_CALL_1(SBI_SEND_IPI, hart_mask);
+ SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask);
}
static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
{
- SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask);
+ SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask);
}
static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
unsigned long start,
unsigned long size)
{
- SBI_CALL_3(SBI_REMOTE_SFENCE_VMA, hart_mask, start, size);
+ SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask,
+ start, size);
}
static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
@@ -92,7 +94,8 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
unsigned long size,
unsigned long asid)
{
- SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
+ SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask,
+ start, size, asid);
}
#else /* CONFIG_RISCV_SBI */
/* stubs for code that is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
--
2.23.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v5 1/4] RISC-V: Mark existing SBI as 0.1 SBI.
2019-11-26 19:05 ` [PATCH v5 1/4] RISC-V: Mark existing SBI as 0.1 SBI Atish Patra
@ 2019-12-02 23:59 ` Palmer Dabbelt
0 siblings, 0 replies; 15+ messages in thread
From: Palmer Dabbelt @ 2019-12-02 23:59 UTC (permalink / raw)
To: Atish Patra
Cc: aou, alexios.zavras, anup, linux-kernel, rppt, Atish Patra,
Paul Walmsley, linux-riscv, tglx, han_mao
On Tue, 26 Nov 2019 11:05:00 PST (-0800), Atish Patra wrote:
> As per the new SBI specification, current SBI implementation version
> is defined as 0.1 and will be removed/replaced in future. Each of the
> function call in 0.1 is defined as a separate extension which makes
> easier to replace them one at a time.
>
> Rename existing implementation to reflect that. This patch is just
> a preparatory patch for SBI v0.2 and doesn't introduce any functional
> changes.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> arch/riscv/include/asm/sbi.h | 43 +++++++++++++++++++-----------------
> 1 file changed, 23 insertions(+), 20 deletions(-)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 2570c1e683d3..96aaee270ded 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -9,17 +9,17 @@
> #include <linux/types.h>
>
> #ifdef CONFIG_RISCV_SBI
> -#define SBI_SET_TIMER 0
> -#define SBI_CONSOLE_PUTCHAR 1
> -#define SBI_CONSOLE_GETCHAR 2
> -#define SBI_CLEAR_IPI 3
> -#define SBI_SEND_IPI 4
> -#define SBI_REMOTE_FENCE_I 5
> -#define SBI_REMOTE_SFENCE_VMA 6
> -#define SBI_REMOTE_SFENCE_VMA_ASID 7
> -#define SBI_SHUTDOWN 8
> +#define SBI_EXT_0_1_SET_TIMER 0x0
> +#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
> +#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
> +#define SBI_EXT_0_1_CLEAR_IPI 0x3
> +#define SBI_EXT_0_1_SEND_IPI 0x4
> +#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
> +#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
> +#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
> +#define SBI_EXT_0_1_SHUTDOWN 0x8
>
> -#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \
> +#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \
> register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
> register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
> register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
> @@ -43,48 +43,50 @@
>
> static inline void sbi_console_putchar(int ch)
> {
> - SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch);
> + SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch);
> }
>
> static inline int sbi_console_getchar(void)
> {
> - return SBI_CALL_0(SBI_CONSOLE_GETCHAR);
> + return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR);
> }
>
> static inline void sbi_set_timer(uint64_t stime_value)
> {
> #if __riscv_xlen == 32
> - SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32);
> + SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value,
> + stime_value >> 32);
> #else
> - SBI_CALL_1(SBI_SET_TIMER, stime_value);
> + SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value);
> #endif
> }
>
> static inline void sbi_shutdown(void)
> {
> - SBI_CALL_0(SBI_SHUTDOWN);
> + SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN);
> }
>
> static inline void sbi_clear_ipi(void)
> {
> - SBI_CALL_0(SBI_CLEAR_IPI);
> + SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI);
> }
>
> static inline void sbi_send_ipi(const unsigned long *hart_mask)
> {
> - SBI_CALL_1(SBI_SEND_IPI, hart_mask);
> + SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask);
> }
>
> static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
> {
> - SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask);
> + SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask);
> }
>
> static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> unsigned long start,
> unsigned long size)
> {
> - SBI_CALL_3(SBI_REMOTE_SFENCE_VMA, hart_mask, start, size);
> + SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask,
> + start, size);
> }
>
> static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> @@ -92,7 +94,8 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> unsigned long size,
> unsigned long asid)
> {
> - SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
> + SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask,
> + start, size, asid);
> }
> #else /* CONFIG_RISCV_SBI */
> /* stubs for code that is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v5 2/4] RISC-V: Add basic support for SBI v0.2
2019-11-26 19:04 [PATCH v5 0/4] Add support for SBI v0.2 Atish Patra
2019-11-26 19:05 ` [PATCH v5 1/4] RISC-V: Mark existing SBI as 0.1 SBI Atish Patra
@ 2019-11-26 19:05 ` Atish Patra
2019-12-03 21:17 ` Palmer Dabbelt
2019-11-26 19:05 ` [PATCH v5 3/4] RISC-V: Introduce a new config for SBI v0.1 Atish Patra
` (2 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: Atish Patra @ 2019-11-26 19:05 UTC (permalink / raw)
To: linux-kernel
Cc: Albert Ou, Alexios Zavras, Anup Patel, Mike Rapoport,
Atish Patra, Palmer Dabbelt, Paul Walmsley, linux-riscv,
Thomas Gleixner, Mao Han
The SBI v0.2 introduces a base extension which is backward compatible
with v0.1. Implement all helper functions and minimum required SBI
calls from v0.2 for now. All other base extension function will be
added later as per need.
As v0.2 calling convention is backward compatible with v0.1, remove
the v0.1 helper functions and just use v0.2 calling convention.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
arch/riscv/include/asm/sbi.h | 139 ++++++++++----------
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/sbi.c | 247 ++++++++++++++++++++++++++++++++++-
arch/riscv/kernel/setup.c | 2 +
4 files changed, 315 insertions(+), 74 deletions(-)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 96aaee270ded..906438322932 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -9,93 +9,88 @@
#include <linux/types.h>
#ifdef CONFIG_RISCV_SBI
-#define SBI_EXT_0_1_SET_TIMER 0x0
-#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
-#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
-#define SBI_EXT_0_1_CLEAR_IPI 0x3
-#define SBI_EXT_0_1_SEND_IPI 0x4
-#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
-#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
-#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
-#define SBI_EXT_0_1_SHUTDOWN 0x8
+enum sbi_ext_id {
+ SBI_EXT_0_1_SET_TIMER = 0x0,
+ SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
+ SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
+ SBI_EXT_0_1_CLEAR_IPI = 0x3,
+ SBI_EXT_0_1_SEND_IPI = 0x4,
+ SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
+ SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
+ SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
+ SBI_EXT_0_1_SHUTDOWN = 0x8,
+ SBI_EXT_BASE = 0x10,
+};
-#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \
- register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
- register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
- register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
- register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3); \
- register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \
- asm volatile ("ecall" \
- : "+r" (a0) \
- : "r" (a1), "r" (a2), "r" (a3), "r" (a7) \
- : "memory"); \
- a0; \
-})
+enum sbi_ext_base_fid {
+ SBI_BASE_GET_SPEC_VERSION = 0,
+ SBI_BASE_GET_IMP_ID,
+ SBI_BASE_GET_IMP_VERSION,
+ SBI_BASE_PROBE_EXT,
+ SBI_BASE_GET_MVENDORID,
+ SBI_BASE_GET_MARCHID,
+ SBI_BASE_GET_MIMPID,
+};
-/* Lazy implementations until SBI is finalized */
-#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0, 0)
-#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0, 0)
-#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0, 0)
-#define SBI_CALL_3(which, arg0, arg1, arg2) \
- SBI_CALL(which, arg0, arg1, arg2, 0)
-#define SBI_CALL_4(which, arg0, arg1, arg2, arg3) \
- SBI_CALL(which, arg0, arg1, arg2, arg3)
+#define SBI_SPEC_VERSION_DEFAULT 0x1
+#define SBI_SPEC_VERSION_MAJOR_OFFSET 24
+#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
+#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
-static inline void sbi_console_putchar(int ch)
-{
- SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch);
-}
+/* SBI return error codes */
+#define SBI_SUCCESS 0
+#define SBI_ERR_FAILURE -1
+#define SBI_ERR_NOT_SUPPORTED -2
+#define SBI_ERR_INVALID_PARAM -3
+#define SBI_ERR_DENIED -4
+#define SBI_ERR_INVALID_ADDRESS -5
-static inline int sbi_console_getchar(void)
-{
- return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR);
-}
+extern unsigned long sbi_spec_version;
+struct sbiret {
+ long error;
+ long value;
+};
-static inline void sbi_set_timer(uint64_t stime_value)
-{
-#if __riscv_xlen == 32
- SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value,
- stime_value >> 32);
-#else
- SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value);
-#endif
-}
-
-static inline void sbi_shutdown(void)
-{
- SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN);
-}
+int sbi_init(void);
+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
+ unsigned long arg1, unsigned long arg2,
+ unsigned long arg3, unsigned long arg4,
+ unsigned long arg5);
-static inline void sbi_clear_ipi(void)
-{
- SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI);
-}
+void sbi_console_putchar(int ch);
+int sbi_console_getchar(void);
+void sbi_set_timer(uint64_t stime_value);
+void sbi_shutdown(void);
+void sbi_clear_ipi(void);
+void sbi_send_ipi(const unsigned long *hart_mask);
+void sbi_remote_fence_i(const unsigned long *hart_mask);
+void sbi_remote_sfence_vma(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size);
-static inline void sbi_send_ipi(const unsigned long *hart_mask)
-{
- SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask);
-}
+void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size,
+ unsigned long asid);
+int sbi_probe_extension(long ext);
-static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
+/* Check if current SBI specification version is 0.1 or not */
+static inline int sbi_spec_is_0_1(void)
{
- SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask);
+ return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0;
}
-static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
- unsigned long start,
- unsigned long size)
+/* Get the major version of SBI */
+static inline unsigned long sbi_major_version(void)
{
- SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask,
- start, size);
+ return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_OFFSET) &
+ SBI_SPEC_VERSION_MAJOR_MASK;
}
-static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
- unsigned long start,
- unsigned long size,
- unsigned long asid)
+/* Get the minor version of SBI */
+static inline unsigned long sbi_minor_version(void)
{
- SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask,
- start, size, asid);
+ return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK;
}
#else /* CONFIG_RISCV_SBI */
/* stubs for code that is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index f40205cb9a22..56127dd359f1 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -17,6 +17,7 @@ obj-y += irq.o
obj-y += process.o
obj-y += ptrace.o
obj-y += reset.o
+obj-y += sbi.o
obj-y += setup.o
obj-y += signal.o
obj-y += syscall_table.o
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index f6c7c3e82d28..a47e23c3a2e1 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -4,14 +4,257 @@
#include <linux/pm.h>
#include <asm/sbi.h>
+/* default SBI version is 0.1 */
+unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
+EXPORT_SYMBOL(sbi_spec_version);
+
+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
+ unsigned long arg1, unsigned long arg2,
+ unsigned long arg3, unsigned long arg4,
+ unsigned long arg5)
+{
+ struct sbiret ret;
+
+ register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
+ register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
+ register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
+ register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
+ register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
+ register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
+ register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
+ register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
+ asm volatile ("ecall"
+ : "+r" (a0), "+r" (a1)
+ : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
+ : "memory");
+ ret.error = a0;
+ ret.value = a1;
+
+ return ret;
+}
+EXPORT_SYMBOL(sbi_ecall);
+
+static int sbi_err_map_linux_errno(int err)
+{
+ switch (err) {
+ case SBI_SUCCESS:
+ return 0;
+ case SBI_ERR_DENIED:
+ return -EPERM;
+ case SBI_ERR_INVALID_PARAM:
+ return -EINVAL;
+ case SBI_ERR_INVALID_ADDRESS:
+ return -EFAULT;
+ case SBI_ERR_NOT_SUPPORTED:
+ case SBI_ERR_FAILURE:
+ default:
+ return -ENOTSUPP;
+ };
+}
+
+/**
+ * sbi_console_putchar() - Writes given character to the console device.
+ * @ch: The data to be written to the console.
+ *
+ * Return: None
+ */
+void sbi_console_putchar(int ch)
+{
+ sbi_ecall(SBI_EXT_0_1_CONSOLE_PUTCHAR, 0, ch, 0, 0, 0, 0, 0);
+}
+EXPORT_SYMBOL(sbi_console_putchar);
+
+/**
+ * sbi_console_getchar() - Reads a byte from console device.
+ *
+ * Returns the value read from console.
+ */
+int sbi_console_getchar(void)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_0_1_CONSOLE_GETCHAR, 0, 0, 0, 0, 0, 0, 0);
+
+ return ret.error;
+}
+EXPORT_SYMBOL(sbi_console_getchar);
+
+/**
+ * sbi_set_timer() - Program the timer for next timer event.
+ * @stime_value: The value after which next timer event should fire.
+ *
+ * Return: None
+ */
+void sbi_set_timer(uint64_t stime_value)
+{
+#if __riscv_xlen == 32
+ sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
+ stime_value >> 32, 0, 0, 0, 0);
+#else
+ sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
+#endif
+}
+EXPORT_SYMBOL(sbi_set_timer);
+
+/**
+ * sbi_shutdown() - Remove all the harts from executing supervisor code.
+ *
+ * Return: None
+ */
+void sbi_shutdown(void)
+{
+ sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
+}
+EXPORT_SYMBOL(sbi_shutdown);
+
+/**
+ * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
+ *
+ * Return: None
+ */
+void sbi_clear_ipi(void)
+{
+ sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
+}
+
+/**
+ * sbi_send_ipi() - Send an IPI to any hart.
+ * @hart_mask: A cpu mask containing all the target harts.
+ *
+ * Return: None
+ */
+void sbi_send_ipi(const unsigned long *hart_mask)
+{
+ sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
+ 0, 0, 0, 0, 0);
+}
+EXPORT_SYMBOL(sbi_send_ipi);
+
+/**
+ * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
+ * @hart_mask: A cpu mask containing all the target harts.
+ *
+ * Return: None
+ */
+void sbi_remote_fence_i(const unsigned long *hart_mask)
+{
+ sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask,
+ 0, 0, 0, 0, 0);
+}
+EXPORT_SYMBOL(sbi_remote_fence_i);
+
+/**
+ * sbi_remote_sfence_vma() - Execute SFENCE.VMA instructions on given remote
+ * harts for the specified virtual address range.
+ * @hart_mask: A cpu mask containing all the target harts.
+ * @start: Start of the virtual address
+ * @size: Total size of the virtual address range.
+ *
+ * Return: None
+ */
+void sbi_remote_sfence_vma(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size)
+{
+ sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
+ (unsigned long)hart_mask, start, size, 0, 0, 0);
+}
+EXPORT_SYMBOL(sbi_remote_sfence_vma);
+
+/**
+ * sbi_remote_sfence_vma_asid() - Execute SFENCE.VMA instructions on given
+ * remote harts for a virtual address range belonging to a specific ASID.
+ *
+ * @hart_mask: A cpu mask containing all the target harts.
+ * @start: Start of the virtual address
+ * @size: Total size of the virtual address range.
+ * @asid: The value of address space identifier (ASID).
+ *
+ * Return: None
+ */
+void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size,
+ unsigned long asid)
+{
+ sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
+ (unsigned long)hart_mask, start, size, asid, 0, 0);
+}
+EXPORT_SYMBOL(sbi_remote_sfence_vma_asid);
+
+/**
+ * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
+ * @extid: The extension ID to be probed.
+ *
+ * Return: Extension specific nonzero value f yes, -ENOTSUPP otherwise.
+ */
+int sbi_probe_extension(long extid)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_BASE_PROBE_EXT, extid, 0, 0, 0, 0, 0);
+ if (!ret.error)
+ if (ret.value)
+ return ret.value;
+
+ return -ENOTSUPP;
+}
+EXPORT_SYMBOL(sbi_probe_extension);
+
+static long sbi_get_spec_version(void)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_BASE_GET_SPEC_VERSION,
+ 0, 0, 0, 0, 0, 0);
+ if (!ret.error)
+ return ret.value;
+ else
+ return ret.error;
+}
+
+static long sbi_get_firmware_id(void)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_BASE_GET_IMP_ID,
+ 0, 0, 0, 0, 0, 0);
+ if (!ret.error)
+ return ret.value;
+ else
+ return sbi_err_map_linux_errno(ret.error);
+}
+
+static long sbi_get_firmware_version(void)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_BASE_GET_IMP_VERSION,
+ 0, 0, 0, 0, 0, 0);
+ if (!ret.error)
+ return ret.value;
+ else
+ return sbi_err_map_linux_errno(ret.error);
+}
+
static void sbi_power_off(void)
{
sbi_shutdown();
}
-static int __init sbi_init(void)
+int __init sbi_init(void)
{
+ int ret;
+
pm_power_off = sbi_power_off;
+ ret = sbi_get_spec_version();
+ if (ret > 0)
+ sbi_spec_version = ret;
+
+ pr_info("SBI specification v%lu.%lu detected\n",
+ sbi_major_version(), sbi_minor_version());
+ if (!sbi_spec_is_0_1())
+ pr_info("SBI implementation ID=0x%lx Version=0x%lx\n",
+ sbi_get_firmware_id(), sbi_get_firmware_version());
return 0;
}
-early_initcall(sbi_init);
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index 365ff8420bfe..f0a3c51e3d1b 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -22,6 +22,7 @@
#include <asm/sections.h>
#include <asm/pgtable.h>
#include <asm/smp.h>
+#include <asm/sbi.h>
#include <asm/tlbflush.h>
#include <asm/thread_info.h>
@@ -74,6 +75,7 @@ void __init setup_arch(char **cmdline_p)
swiotlb_init(1);
#endif
+ sbi_init();
#ifdef CONFIG_SMP
setup_smp();
#endif
--
2.23.0
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v5 2/4] RISC-V: Add basic support for SBI v0.2
2019-11-26 19:05 ` [PATCH v5 2/4] RISC-V: Add basic support for SBI v0.2 Atish Patra
@ 2019-12-03 21:17 ` Palmer Dabbelt
0 siblings, 0 replies; 15+ messages in thread
From: Palmer Dabbelt @ 2019-12-03 21:17 UTC (permalink / raw)
To: Atish Patra
Cc: aou, alexios.zavras, anup, linux-kernel, rppt, Atish Patra,
Paul Walmsley, linux-riscv, tglx, han_mao
On Tue, 26 Nov 2019 11:05:01 PST (-0800), Atish Patra wrote:
> The SBI v0.2 introduces a base extension which is backward compatible
> with v0.1. Implement all helper functions and minimum required SBI
> calls from v0.2 for now. All other base extension function will be
> added later as per need.
> As v0.2 calling convention is backward compatible with v0.1, remove
> the v0.1 helper functions and just use v0.2 calling convention.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> arch/riscv/include/asm/sbi.h | 139 ++++++++++----------
> arch/riscv/kernel/Makefile | 1 +
> arch/riscv/kernel/sbi.c | 247 ++++++++++++++++++++++++++++++++++-
> arch/riscv/kernel/setup.c | 2 +
> 4 files changed, 315 insertions(+), 74 deletions(-)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 96aaee270ded..906438322932 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -9,93 +9,88 @@
> #include <linux/types.h>
>
> #ifdef CONFIG_RISCV_SBI
> -#define SBI_EXT_0_1_SET_TIMER 0x0
> -#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
> -#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
> -#define SBI_EXT_0_1_CLEAR_IPI 0x3
> -#define SBI_EXT_0_1_SEND_IPI 0x4
> -#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
> -#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
> -#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
> -#define SBI_EXT_0_1_SHUTDOWN 0x8
> +enum sbi_ext_id {
> + SBI_EXT_0_1_SET_TIMER = 0x0,
> + SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
> + SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
> + SBI_EXT_0_1_CLEAR_IPI = 0x3,
> + SBI_EXT_0_1_SEND_IPI = 0x4,
> + SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
> + SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
> + SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
> + SBI_EXT_0_1_SHUTDOWN = 0x8,
> + SBI_EXT_BASE = 0x10,
> +};
>
> -#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \
> - register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
> - register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
> - register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
> - register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3); \
> - register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \
> - asm volatile ("ecall" \
> - : "+r" (a0) \
> - : "r" (a1), "r" (a2), "r" (a3), "r" (a7) \
> - : "memory"); \
> - a0; \
> -})
> +enum sbi_ext_base_fid {
> + SBI_BASE_GET_SPEC_VERSION = 0,
> + SBI_BASE_GET_IMP_ID,
> + SBI_BASE_GET_IMP_VERSION,
> + SBI_BASE_PROBE_EXT,
> + SBI_BASE_GET_MVENDORID,
> + SBI_BASE_GET_MARCHID,
> + SBI_BASE_GET_MIMPID,
> +};
>
> -/* Lazy implementations until SBI is finalized */
> -#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0, 0)
> -#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0, 0)
> -#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0, 0)
> -#define SBI_CALL_3(which, arg0, arg1, arg2) \
> - SBI_CALL(which, arg0, arg1, arg2, 0)
> -#define SBI_CALL_4(which, arg0, arg1, arg2, arg3) \
> - SBI_CALL(which, arg0, arg1, arg2, arg3)
> +#define SBI_SPEC_VERSION_DEFAULT 0x1
> +#define SBI_SPEC_VERSION_MAJOR_OFFSET 24
> +#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
> +#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
>
> -static inline void sbi_console_putchar(int ch)
> -{
> - SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch);
> -}
> +/* SBI return error codes */
> +#define SBI_SUCCESS 0
> +#define SBI_ERR_FAILURE -1
> +#define SBI_ERR_NOT_SUPPORTED -2
> +#define SBI_ERR_INVALID_PARAM -3
> +#define SBI_ERR_DENIED -4
> +#define SBI_ERR_INVALID_ADDRESS -5
>
> -static inline int sbi_console_getchar(void)
> -{
> - return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR);
> -}
> +extern unsigned long sbi_spec_version;
> +struct sbiret {
> + long error;
> + long value;
> +};
>
> -static inline void sbi_set_timer(uint64_t stime_value)
> -{
> -#if __riscv_xlen == 32
> - SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value,
> - stime_value >> 32);
> -#else
> - SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value);
> -#endif
> -}
> -
> -static inline void sbi_shutdown(void)
> -{
> - SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN);
> -}
> +int sbi_init(void);
> +struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> + unsigned long arg1, unsigned long arg2,
> + unsigned long arg3, unsigned long arg4,
> + unsigned long arg5);
>
> -static inline void sbi_clear_ipi(void)
> -{
> - SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI);
> -}
> +void sbi_console_putchar(int ch);
> +int sbi_console_getchar(void);
> +void sbi_set_timer(uint64_t stime_value);
> +void sbi_shutdown(void);
> +void sbi_clear_ipi(void);
> +void sbi_send_ipi(const unsigned long *hart_mask);
> +void sbi_remote_fence_i(const unsigned long *hart_mask);
> +void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size);
>
> -static inline void sbi_send_ipi(const unsigned long *hart_mask)
> -{
> - SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask);
> -}
> +void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size,
> + unsigned long asid);
> +int sbi_probe_extension(long ext);
>
> -static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
> +/* Check if current SBI specification version is 0.1 or not */
> +static inline int sbi_spec_is_0_1(void)
> {
> - SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask);
> + return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0;
> }
>
> -static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> - unsigned long start,
> - unsigned long size)
> +/* Get the major version of SBI */
> +static inline unsigned long sbi_major_version(void)
> {
> - SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask,
> - start, size);
> + return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_OFFSET) &
> + SBI_SPEC_VERSION_MAJOR_MASK;
> }
>
> -static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> - unsigned long start,
> - unsigned long size,
> - unsigned long asid)
> +/* Get the minor version of SBI */
> +static inline unsigned long sbi_minor_version(void)
> {
> - SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask,
> - start, size, asid);
> + return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK;
> }
> #else /* CONFIG_RISCV_SBI */
> /* stubs for code that is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
> diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> index f40205cb9a22..56127dd359f1 100644
> --- a/arch/riscv/kernel/Makefile
> +++ b/arch/riscv/kernel/Makefile
> @@ -17,6 +17,7 @@ obj-y += irq.o
> obj-y += process.o
> obj-y += ptrace.o
> obj-y += reset.o
> +obj-y += sbi.o
> obj-y += setup.o
> obj-y += signal.o
> obj-y += syscall_table.o
> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> index f6c7c3e82d28..a47e23c3a2e1 100644
> --- a/arch/riscv/kernel/sbi.c
> +++ b/arch/riscv/kernel/sbi.c
> @@ -4,14 +4,257 @@
> #include <linux/pm.h>
> #include <asm/sbi.h>
>
> +/* default SBI version is 0.1 */
> +unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
> +EXPORT_SYMBOL(sbi_spec_version);
> +
> +struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> + unsigned long arg1, unsigned long arg2,
> + unsigned long arg3, unsigned long arg4,
> + unsigned long arg5)
> +{
> + struct sbiret ret;
> +
> + register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
> + register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
> + register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
> + register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
> + register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
> + register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
> + register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
> + register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
> + asm volatile ("ecall"
> + : "+r" (a0), "+r" (a1)
> + : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
> + : "memory");
> + ret.error = a0;
> + ret.value = a1;
> +
> + return ret;
> +}
> +EXPORT_SYMBOL(sbi_ecall);
> +
> +static int sbi_err_map_linux_errno(int err)
> +{
> + switch (err) {
> + case SBI_SUCCESS:
> + return 0;
> + case SBI_ERR_DENIED:
> + return -EPERM;
> + case SBI_ERR_INVALID_PARAM:
> + return -EINVAL;
> + case SBI_ERR_INVALID_ADDRESS:
> + return -EFAULT;
> + case SBI_ERR_NOT_SUPPORTED:
> + case SBI_ERR_FAILURE:
> + default:
> + return -ENOTSUPP;
> + };
> +}
> +
> +/**
> + * sbi_console_putchar() - Writes given character to the console device.
> + * @ch: The data to be written to the console.
> + *
> + * Return: None
> + */
> +void sbi_console_putchar(int ch)
> +{
> + sbi_ecall(SBI_EXT_0_1_CONSOLE_PUTCHAR, 0, ch, 0, 0, 0, 0, 0);
> +}
> +EXPORT_SYMBOL(sbi_console_putchar);
> +
> +/**
> + * sbi_console_getchar() - Reads a byte from console device.
> + *
> + * Returns the value read from console.
> + */
> +int sbi_console_getchar(void)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_0_1_CONSOLE_GETCHAR, 0, 0, 0, 0, 0, 0, 0);
> +
> + return ret.error;
> +}
> +EXPORT_SYMBOL(sbi_console_getchar);
> +
> +/**
> + * sbi_set_timer() - Program the timer for next timer event.
> + * @stime_value: The value after which next timer event should fire.
> + *
> + * Return: None
> + */
> +void sbi_set_timer(uint64_t stime_value)
> +{
> +#if __riscv_xlen == 32
> + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
> + stime_value >> 32, 0, 0, 0, 0);
> +#else
> + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
> +#endif
> +}
> +EXPORT_SYMBOL(sbi_set_timer);
> +
> +/**
> + * sbi_shutdown() - Remove all the harts from executing supervisor code.
> + *
> + * Return: None
> + */
> +void sbi_shutdown(void)
> +{
> + sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
> +}
> +EXPORT_SYMBOL(sbi_shutdown);
> +
> +/**
> + * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
> + *
> + * Return: None
> + */
> +void sbi_clear_ipi(void)
> +{
> + sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
> +}
> +
> +/**
> + * sbi_send_ipi() - Send an IPI to any hart.
> + * @hart_mask: A cpu mask containing all the target harts.
> + *
> + * Return: None
> + */
> +void sbi_send_ipi(const unsigned long *hart_mask)
> +{
> + sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
> + 0, 0, 0, 0, 0);
> +}
> +EXPORT_SYMBOL(sbi_send_ipi);
> +
> +/**
> + * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
> + * @hart_mask: A cpu mask containing all the target harts.
> + *
> + * Return: None
> + */
> +void sbi_remote_fence_i(const unsigned long *hart_mask)
> +{
> + sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask,
> + 0, 0, 0, 0, 0);
> +}
> +EXPORT_SYMBOL(sbi_remote_fence_i);
> +
> +/**
> + * sbi_remote_sfence_vma() - Execute SFENCE.VMA instructions on given remote
> + * harts for the specified virtual address range.
> + * @hart_mask: A cpu mask containing all the target harts.
> + * @start: Start of the virtual address
> + * @size: Total size of the virtual address range.
> + *
> + * Return: None
> + */
> +void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size)
> +{
> + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
> + (unsigned long)hart_mask, start, size, 0, 0, 0);
> +}
> +EXPORT_SYMBOL(sbi_remote_sfence_vma);
> +
> +/**
> + * sbi_remote_sfence_vma_asid() - Execute SFENCE.VMA instructions on given
> + * remote harts for a virtual address range belonging to a specific ASID.
> + *
> + * @hart_mask: A cpu mask containing all the target harts.
> + * @start: Start of the virtual address
> + * @size: Total size of the virtual address range.
> + * @asid: The value of address space identifier (ASID).
> + *
> + * Return: None
> + */
> +void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size,
> + unsigned long asid)
> +{
> + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
> + (unsigned long)hart_mask, start, size, asid, 0, 0);
> +}
> +EXPORT_SYMBOL(sbi_remote_sfence_vma_asid);
> +
> +/**
> + * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
> + * @extid: The extension ID to be probed.
> + *
> + * Return: Extension specific nonzero value f yes, -ENOTSUPP otherwise.
> + */
> +int sbi_probe_extension(long extid)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_BASE, SBI_BASE_PROBE_EXT, extid, 0, 0, 0, 0, 0);
> + if (!ret.error)
> + if (ret.value)
> + return ret.value;
> +
> + return -ENOTSUPP;
> +}
> +EXPORT_SYMBOL(sbi_probe_extension);
> +
> +static long sbi_get_spec_version(void)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_BASE, SBI_BASE_GET_SPEC_VERSION,
> + 0, 0, 0, 0, 0, 0);
> + if (!ret.error)
> + return ret.value;
> + else
> + return ret.error;
> +}
> +
> +static long sbi_get_firmware_id(void)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_BASE, SBI_BASE_GET_IMP_ID,
> + 0, 0, 0, 0, 0, 0);
> + if (!ret.error)
> + return ret.value;
> + else
> + return sbi_err_map_linux_errno(ret.error);
> +}
> +
> +static long sbi_get_firmware_version(void)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_BASE, SBI_BASE_GET_IMP_VERSION,
> + 0, 0, 0, 0, 0, 0);
> + if (!ret.error)
> + return ret.value;
> + else
> + return sbi_err_map_linux_errno(ret.error);
> +}
> +
> static void sbi_power_off(void)
> {
> sbi_shutdown();
> }
>
> -static int __init sbi_init(void)
> +int __init sbi_init(void)
> {
> + int ret;
> +
> pm_power_off = sbi_power_off;
> + ret = sbi_get_spec_version();
> + if (ret > 0)
> + sbi_spec_version = ret;
> +
> + pr_info("SBI specification v%lu.%lu detected\n",
> + sbi_major_version(), sbi_minor_version());
> + if (!sbi_spec_is_0_1())
> + pr_info("SBI implementation ID=0x%lx Version=0x%lx\n",
> + sbi_get_firmware_id(), sbi_get_firmware_version());
> return 0;
> }
> -early_initcall(sbi_init);
> diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> index 365ff8420bfe..f0a3c51e3d1b 100644
> --- a/arch/riscv/kernel/setup.c
> +++ b/arch/riscv/kernel/setup.c
> @@ -22,6 +22,7 @@
> #include <asm/sections.h>
> #include <asm/pgtable.h>
> #include <asm/smp.h>
> +#include <asm/sbi.h>
> #include <asm/tlbflush.h>
> #include <asm/thread_info.h>
>
> @@ -74,6 +75,7 @@ void __init setup_arch(char **cmdline_p)
> swiotlb_init(1);
> #endif
>
> + sbi_init();
> #ifdef CONFIG_SMP
> setup_smp();
> #endif
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v5 3/4] RISC-V: Introduce a new config for SBI v0.1
2019-11-26 19:04 [PATCH v5 0/4] Add support for SBI v0.2 Atish Patra
2019-11-26 19:05 ` [PATCH v5 1/4] RISC-V: Mark existing SBI as 0.1 SBI Atish Patra
2019-11-26 19:05 ` [PATCH v5 2/4] RISC-V: Add basic support for SBI v0.2 Atish Patra
@ 2019-11-26 19:05 ` Atish Patra
2019-12-04 18:52 ` Palmer Dabbelt
2019-11-26 19:05 ` [PATCH v5 4/4] RISC-V: Implement new SBI v0.2 extensions Atish Patra
2019-12-04 18:56 ` [PATCH v5 0/4] Add support for SBI v0.2 Palmer Dabbelt
4 siblings, 1 reply; 15+ messages in thread
From: Atish Patra @ 2019-11-26 19:05 UTC (permalink / raw)
To: linux-kernel
Cc: Albert Ou, Alexios Zavras, Anup Patel, Mike Rapoport,
Atish Patra, Palmer Dabbelt, Paul Walmsley, linux-riscv,
Thomas Gleixner, Mao Han
We now have SBI v0.2 which is more scalable and extendable to handle
future needs for RISC-V supervisor interfaces.
Introduce a new config and move all SBI v0.1 code under that config.
This allows to implement the new replacement SBI extensions cleanly
and remove v0.1 extensions easily in future. Currently, the config
is enabled by default. Once all M-mode software with v0.1 are no
longer in use, this config option and all relevant code can be easily
removed.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
arch/riscv/Kconfig | 6 ++
arch/riscv/include/asm/sbi.h | 2 +
arch/riscv/kernel/sbi.c | 154 +++++++++++++++++++++++++++++------
3 files changed, 138 insertions(+), 24 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ca3b5541ae93..15c020d6837b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -304,6 +304,12 @@ config SECCOMP
and the task is only allowed to execute a few safe syscalls
defined by each seccomp mode.
+config RISCV_SBI_V01
+ bool "SBI v0.1 support"
+ default y
+ help
+ This config allows kernel to use SBI v0.1 APIs. This will be
+ deprecated in future once legacy M-mode software are no longer in use.
endmenu
menu "Boot options"
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 906438322932..cc82ae63f8e0 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -10,6 +10,7 @@
#ifdef CONFIG_RISCV_SBI
enum sbi_ext_id {
+#ifdef CONFIG_RISCV_SBI_V01
SBI_EXT_0_1_SET_TIMER = 0x0,
SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
@@ -19,6 +20,7 @@ enum sbi_ext_id {
SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
SBI_EXT_0_1_SHUTDOWN = 0x8,
+#endif
SBI_EXT_BASE = 0x10,
};
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index a47e23c3a2e1..ee710bfe0b0e 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -8,6 +8,14 @@
unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
EXPORT_SYMBOL(sbi_spec_version);
+static void (*__sbi_set_timer)(uint64_t stime);
+static int (*__sbi_send_ipi)(const unsigned long *hart_mask);
+static int (*__sbi_rfence)(unsigned long extid, unsigned long fid,
+ const unsigned long *hart_mask,
+ unsigned long hbase, unsigned long start,
+ unsigned long size, unsigned long arg4,
+ unsigned long arg5);
+
struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
unsigned long arg1, unsigned long arg2,
unsigned long arg3, unsigned long arg4,
@@ -52,6 +60,32 @@ static int sbi_err_map_linux_errno(int err)
};
}
+static void __sbi_set_timer_dummy_warn(uint64_t stime_value)
+{
+ pr_warn("Timer extension is not available in SBI v%lu.%lu\n",
+ sbi_major_version(), sbi_minor_version());
+}
+
+static int __sbi_send_ipi_dummy_warn(const unsigned long *hart_mask)
+{
+ pr_warn("IPI extension is not available in SBI v%lu.%lu\n",
+ sbi_major_version(), sbi_minor_version());
+ return 0;
+}
+
+static int __sbi_rfence_dummy_warn(unsigned long extid,
+ unsigned long fid,
+ const unsigned long *hart_mask,
+ unsigned long hbase, unsigned long start,
+ unsigned long size, unsigned long arg4,
+ unsigned long arg5)
+{
+ pr_warn("remote fence extension is not available in SBI v%lu.%lu\n",
+ sbi_major_version(), sbi_minor_version());
+ return 0;
+}
+
+#ifdef CONFIG_RISCV_SBI_V01
/**
* sbi_console_putchar() - Writes given character to the console device.
* @ch: The data to be written to the console.
@@ -80,41 +114,106 @@ int sbi_console_getchar(void)
EXPORT_SYMBOL(sbi_console_getchar);
/**
- * sbi_set_timer() - Program the timer for next timer event.
- * @stime_value: The value after which next timer event should fire.
+ * sbi_shutdown() - Remove all the harts from executing supervisor code.
*
* Return: None
*/
-void sbi_set_timer(uint64_t stime_value)
+void sbi_shutdown(void)
{
-#if __riscv_xlen == 32
- sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
- stime_value >> 32, 0, 0, 0, 0);
-#else
- sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
-#endif
+ sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
}
EXPORT_SYMBOL(sbi_set_timer);
/**
- * sbi_shutdown() - Remove all the harts from executing supervisor code.
+ * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
*
* Return: None
*/
-void sbi_shutdown(void)
+void sbi_clear_ipi(void)
{
- sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
+ sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
}
EXPORT_SYMBOL(sbi_shutdown);
/**
- * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
+ * sbi_set_timer_v01() - Program the timer for next timer event.
+ * @stime_value: The value after which next timer event should fire.
*
* Return: None
*/
-void sbi_clear_ipi(void)
+static void __sbi_set_timer_v01(uint64_t stime_value)
{
- sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
+#if __riscv_xlen == 32
+ sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
+ stime_value >> 32, 0, 0, 0, 0);
+#else
+ sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
+#endif
+}
+
+static int __sbi_send_ipi_v01(const unsigned long *hart_mask)
+{
+ sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
+ 0, 0, 0, 0, 0);
+ return 0;
+}
+
+static int __sbi_rfence_v01(unsigned long ext, unsigned long fid,
+ const unsigned long *hart_mask,
+ unsigned long hbase, unsigned long start,
+ unsigned long size, unsigned long arg4,
+ unsigned long arg5)
+{
+ switch (ext) {
+ case SBI_EXT_0_1_REMOTE_FENCE_I:
+ sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0,
+ (unsigned long)hart_mask, 0, 0, 0, 0, 0);
+ break;
+ case SBI_EXT_0_1_REMOTE_SFENCE_VMA:
+ sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
+ (unsigned long)hart_mask, start, size,
+ 0, 0, 0);
+ break;
+ case SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID:
+ sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
+ (unsigned long)hart_mask, start, size,
+ arg4, 0, 0);
+ break;
+ default:
+ pr_err("extid [%lu]not supported in SBI v0.1\n", ext);
+ }
+
+ return 0;
+}
+#else
+static void __sbi_set_timer_v01(uint64_t stime_value)
+{
+ __sbi_set_timer_dummy_warn(0);
+}
+static int __sbi_send_ipi_v01(const unsigned long *hart_mask)
+{
+ return __sbi_send_ipi_dummy_warn(NULL);
+}
+static int __sbi_rfence_v01(unsigned long ext, unsigned long fid,
+ const unsigned long *hart_mask,
+ unsigned long hbase, unsigned long start,
+ unsigned long size, unsigned long arg4,
+ unsigned long arg5)
+{
+ return __sbi_rfence_dummy_warn(0, 0, 0, 0, 0, 0, 0, 0);
+
+}
+#endif /* CONFIG_RISCV_SBI_V01 */
+
+/**
+ * sbi_set_timer() - Program the timer for next timer event.
+ * @stime_value: The value after which next timer event should fire.
+ *
+ * Return: None
+ */
+void sbi_set_timer(uint64_t stime_value)
+{
+ __sbi_set_timer(stime_value);
}
/**
@@ -125,11 +224,11 @@ void sbi_clear_ipi(void)
*/
void sbi_send_ipi(const unsigned long *hart_mask)
{
- sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
- 0, 0, 0, 0, 0);
+ __sbi_send_ipi(hart_mask);
}
EXPORT_SYMBOL(sbi_send_ipi);
+
/**
* sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
* @hart_mask: A cpu mask containing all the target harts.
@@ -138,8 +237,8 @@ EXPORT_SYMBOL(sbi_send_ipi);
*/
void sbi_remote_fence_i(const unsigned long *hart_mask)
{
- sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask,
- 0, 0, 0, 0, 0);
+ __sbi_rfence(SBI_EXT_0_1_REMOTE_FENCE_I, 0,
+ hart_mask, 0, 0, 0, 0, 0);
}
EXPORT_SYMBOL(sbi_remote_fence_i);
@@ -156,8 +255,8 @@ void sbi_remote_sfence_vma(const unsigned long *hart_mask,
unsigned long start,
unsigned long size)
{
- sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
- (unsigned long)hart_mask, start, size, 0, 0, 0);
+ __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
+ hart_mask, 0, start, size, 0, 0);
}
EXPORT_SYMBOL(sbi_remote_sfence_vma);
@@ -177,8 +276,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
unsigned long size,
unsigned long asid)
{
- sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
- (unsigned long)hart_mask, start, size, asid, 0, 0);
+ __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
+ hart_mask, 0, start, size, asid, 0);
}
EXPORT_SYMBOL(sbi_remote_sfence_vma_asid);
@@ -253,8 +352,15 @@ int __init sbi_init(void)
pr_info("SBI specification v%lu.%lu detected\n",
sbi_major_version(), sbi_minor_version());
- if (!sbi_spec_is_0_1())
+
+ if (!sbi_spec_is_0_1()) {
pr_info("SBI implementation ID=0x%lx Version=0x%lx\n",
sbi_get_firmware_id(), sbi_get_firmware_version());
+ }
+
+ __sbi_set_timer = __sbi_set_timer_v01;
+ __sbi_send_ipi = __sbi_send_ipi_v01;
+ __sbi_rfence = __sbi_rfence_v01;
+
return 0;
}
--
2.23.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v5 3/4] RISC-V: Introduce a new config for SBI v0.1
2019-11-26 19:05 ` [PATCH v5 3/4] RISC-V: Introduce a new config for SBI v0.1 Atish Patra
@ 2019-12-04 18:52 ` Palmer Dabbelt
2019-12-04 22:03 ` Atish Patra
0 siblings, 1 reply; 15+ messages in thread
From: Palmer Dabbelt @ 2019-12-04 18:52 UTC (permalink / raw)
To: Atish Patra
Cc: aou, Atish Patra, anup, linux-kernel, rppt, alexios.zavras,
Paul Walmsley, linux-riscv, tglx, han_mao
On Tue, 26 Nov 2019 11:05:02 PST (-0800), Atish Patra wrote:
> We now have SBI v0.2 which is more scalable and extendable to handle
> future needs for RISC-V supervisor interfaces.
>
> Introduce a new config and move all SBI v0.1 code under that config.
> This allows to implement the new replacement SBI extensions cleanly
> and remove v0.1 extensions easily in future. Currently, the config
> is enabled by default. Once all M-mode software with v0.1 are no
I'd say "software is", not "software are". There's at least one more instance
of this.
> longer in use, this config option and all relevant code can be easily
> removed.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> arch/riscv/Kconfig | 6 ++
> arch/riscv/include/asm/sbi.h | 2 +
> arch/riscv/kernel/sbi.c | 154 +++++++++++++++++++++++++++++------
> 3 files changed, 138 insertions(+), 24 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index ca3b5541ae93..15c020d6837b 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -304,6 +304,12 @@ config SECCOMP
> and the task is only allowed to execute a few safe syscalls
> defined by each seccomp mode.
>
> +config RISCV_SBI_V01
> + bool "SBI v0.1 support"
I don't think presenting this to users as "v0.1" is correct. I'd expect that
to disable probing and assume the legacy extension always exists, while this
just allows the legacy extension to be used in a v0.2 style. For example: it's
checking the SBI version, which doesn't exist in v0.1.
There should really be two options here: one to allow the legacy extension set
and one to be compatible with SBI v0.1. We can deprecate the v0.1 support much
sooner than the legacy extension set.
> + default y
> + help
> + This config allows kernel to use SBI v0.1 APIs. This will be
> + deprecated in future once legacy M-mode software are no longer in use.
> endmenu
>
> menu "Boot options"
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 906438322932..cc82ae63f8e0 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -10,6 +10,7 @@
>
> #ifdef CONFIG_RISCV_SBI
> enum sbi_ext_id {
> +#ifdef CONFIG_RISCV_SBI_V01
> SBI_EXT_0_1_SET_TIMER = 0x0,
> SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
> SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
> @@ -19,6 +20,7 @@ enum sbi_ext_id {
> SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
> SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
> SBI_EXT_0_1_SHUTDOWN = 0x8,
> +#endif
> SBI_EXT_BASE = 0x10,
> };
>
> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> index a47e23c3a2e1..ee710bfe0b0e 100644
> --- a/arch/riscv/kernel/sbi.c
> +++ b/arch/riscv/kernel/sbi.c
> @@ -8,6 +8,14 @@
> unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
> EXPORT_SYMBOL(sbi_spec_version);
>
> +static void (*__sbi_set_timer)(uint64_t stime);
> +static int (*__sbi_send_ipi)(const unsigned long *hart_mask);
> +static int (*__sbi_rfence)(unsigned long extid, unsigned long fid,
> + const unsigned long *hart_mask,
> + unsigned long hbase, unsigned long start,
> + unsigned long size, unsigned long arg4,
> + unsigned long arg5);
> +
> struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> unsigned long arg1, unsigned long arg2,
> unsigned long arg3, unsigned long arg4,
> @@ -52,6 +60,32 @@ static int sbi_err_map_linux_errno(int err)
> };
> }
>
> +static void __sbi_set_timer_dummy_warn(uint64_t stime_value)
> +{
> + pr_warn("Timer extension is not available in SBI v%lu.%lu\n",
> + sbi_major_version(), sbi_minor_version());
> +}
> +
> +static int __sbi_send_ipi_dummy_warn(const unsigned long *hart_mask)
> +{
> + pr_warn("IPI extension is not available in SBI v%lu.%lu\n",
> + sbi_major_version(), sbi_minor_version());
> + return 0;
> +}
> +
> +static int __sbi_rfence_dummy_warn(unsigned long extid,
> + unsigned long fid,
> + const unsigned long *hart_mask,
> + unsigned long hbase, unsigned long start,
> + unsigned long size, unsigned long arg4,
> + unsigned long arg5)
> +{
> + pr_warn("remote fence extension is not available in SBI v%lu.%lu\n",
> + sbi_major_version(), sbi_minor_version());
> + return 0;
> +}
> +
> +#ifdef CONFIG_RISCV_SBI_V01
> /**
> * sbi_console_putchar() - Writes given character to the console device.
> * @ch: The data to be written to the console.
> @@ -80,41 +114,106 @@ int sbi_console_getchar(void)
> EXPORT_SYMBOL(sbi_console_getchar);
>
> /**
> - * sbi_set_timer() - Program the timer for next timer event.
> - * @stime_value: The value after which next timer event should fire.
> + * sbi_shutdown() - Remove all the harts from executing supervisor code.
> *
> * Return: None
> */
> -void sbi_set_timer(uint64_t stime_value)
> +void sbi_shutdown(void)
> {
> -#if __riscv_xlen == 32
> - sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
> - stime_value >> 32, 0, 0, 0, 0);
> -#else
> - sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
> -#endif
> + sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
> }
> EXPORT_SYMBOL(sbi_set_timer);
>
> /**
> - * sbi_shutdown() - Remove all the harts from executing supervisor code.
> + * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
> *
> * Return: None
> */
> -void sbi_shutdown(void)
> +void sbi_clear_ipi(void)
> {
> - sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
> + sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
> }
> EXPORT_SYMBOL(sbi_shutdown);
>
> /**
> - * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
> + * sbi_set_timer_v01() - Program the timer for next timer event.
> + * @stime_value: The value after which next timer event should fire.
> *
> * Return: None
> */
> -void sbi_clear_ipi(void)
> +static void __sbi_set_timer_v01(uint64_t stime_value)
> {
> - sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
> +#if __riscv_xlen == 32
> + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
> + stime_value >> 32, 0, 0, 0, 0);
> +#else
> + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
> +#endif
> +}
> +
> +static int __sbi_send_ipi_v01(const unsigned long *hart_mask)
> +{
> + sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
> + 0, 0, 0, 0, 0);
> + return 0;
> +}
> +
> +static int __sbi_rfence_v01(unsigned long ext, unsigned long fid,
> + const unsigned long *hart_mask,
> + unsigned long hbase, unsigned long start,
> + unsigned long size, unsigned long arg4,
> + unsigned long arg5)
> +{
> + switch (ext) {
> + case SBI_EXT_0_1_REMOTE_FENCE_I:
> + sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0,
> + (unsigned long)hart_mask, 0, 0, 0, 0, 0);
> + break;
> + case SBI_EXT_0_1_REMOTE_SFENCE_VMA:
> + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
> + (unsigned long)hart_mask, start, size,
> + 0, 0, 0);
> + break;
> + case SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID:
> + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
> + (unsigned long)hart_mask, start, size,
> + arg4, 0, 0);
> + break;
> + default:
> + pr_err("extid [%lu]not supported in SBI v0.1\n", ext);
> + }
> +
> + return 0;
> +}
> +#else
> +static void __sbi_set_timer_v01(uint64_t stime_value)
> +{
> + __sbi_set_timer_dummy_warn(0);
> +}
> +static int __sbi_send_ipi_v01(const unsigned long *hart_mask)
> +{
> + return __sbi_send_ipi_dummy_warn(NULL);
> +}
> +static int __sbi_rfence_v01(unsigned long ext, unsigned long fid,
> + const unsigned long *hart_mask,
> + unsigned long hbase, unsigned long start,
> + unsigned long size, unsigned long arg4,
> + unsigned long arg5)
> +{
> + return __sbi_rfence_dummy_warn(0, 0, 0, 0, 0, 0, 0, 0);
> +
> +}
> +#endif /* CONFIG_RISCV_SBI_V01 */
> +
> +/**
> + * sbi_set_timer() - Program the timer for next timer event.
> + * @stime_value: The value after which next timer event should fire.
> + *
> + * Return: None
> + */
> +void sbi_set_timer(uint64_t stime_value)
> +{
> + __sbi_set_timer(stime_value);
> }
>
> /**
> @@ -125,11 +224,11 @@ void sbi_clear_ipi(void)
> */
> void sbi_send_ipi(const unsigned long *hart_mask)
> {
> - sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
> - 0, 0, 0, 0, 0);
> + __sbi_send_ipi(hart_mask);
> }
> EXPORT_SYMBOL(sbi_send_ipi);
>
> +
> /**
> * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
> * @hart_mask: A cpu mask containing all the target harts.
> @@ -138,8 +237,8 @@ EXPORT_SYMBOL(sbi_send_ipi);
> */
> void sbi_remote_fence_i(const unsigned long *hart_mask)
> {
> - sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask,
> - 0, 0, 0, 0, 0);
> + __sbi_rfence(SBI_EXT_0_1_REMOTE_FENCE_I, 0,
> + hart_mask, 0, 0, 0, 0, 0);
> }
> EXPORT_SYMBOL(sbi_remote_fence_i);
>
> @@ -156,8 +255,8 @@ void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> unsigned long start,
> unsigned long size)
> {
> - sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
> - (unsigned long)hart_mask, start, size, 0, 0, 0);
> + __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
> + hart_mask, 0, start, size, 0, 0);
> }
> EXPORT_SYMBOL(sbi_remote_sfence_vma);
>
> @@ -177,8 +276,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> unsigned long size,
> unsigned long asid)
> {
> - sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
> - (unsigned long)hart_mask, start, size, asid, 0, 0);
> + __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
> + hart_mask, 0, start, size, asid, 0);
> }
> EXPORT_SYMBOL(sbi_remote_sfence_vma_asid);
>
> @@ -253,8 +352,15 @@ int __init sbi_init(void)
>
> pr_info("SBI specification v%lu.%lu detected\n",
> sbi_major_version(), sbi_minor_version());
> - if (!sbi_spec_is_0_1())
> +
> + if (!sbi_spec_is_0_1()) {
> pr_info("SBI implementation ID=0x%lx Version=0x%lx\n",
> sbi_get_firmware_id(), sbi_get_firmware_version());
> + }
> +
> + __sbi_set_timer = __sbi_set_timer_v01;
> + __sbi_send_ipi = __sbi_send_ipi_v01;
> + __sbi_rfence = __sbi_rfence_v01;
> +
> return 0;
> }
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v5 3/4] RISC-V: Introduce a new config for SBI v0.1
2019-12-04 18:52 ` Palmer Dabbelt
@ 2019-12-04 22:03 ` Atish Patra
0 siblings, 0 replies; 15+ messages in thread
From: Atish Patra @ 2019-12-04 22:03 UTC (permalink / raw)
To: palmerdabbelt
Cc: aou, anup, linux-kernel, rppt, alexios.zavras, paul.walmsley,
linux-riscv, tglx, han_mao
On Wed, 2019-12-04 at 10:52 -0800, Palmer Dabbelt wrote:
> On Tue, 26 Nov 2019 11:05:02 PST (-0800), Atish Patra wrote:
> > We now have SBI v0.2 which is more scalable and extendable to
> > handle
> > future needs for RISC-V supervisor interfaces.
> >
> > Introduce a new config and move all SBI v0.1 code under that
> > config.
> > This allows to implement the new replacement SBI extensions cleanly
> > and remove v0.1 extensions easily in future. Currently, the config
> > is enabled by default. Once all M-mode software with v0.1 are no
>
> I'd say "software is", not "software are". There's at least one more
> instance
> of this.
>
Sure. Wil fix this.
> > longer in use, this config option and all relevant code can be
> > easily
> > removed.
> >
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > Reviewed-by: Anup Patel <anup@brainfault.org>
> > ---
> > arch/riscv/Kconfig | 6 ++
> > arch/riscv/include/asm/sbi.h | 2 +
> > arch/riscv/kernel/sbi.c | 154 +++++++++++++++++++++++++++++
> > ------
> > 3 files changed, 138 insertions(+), 24 deletions(-)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index ca3b5541ae93..15c020d6837b 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -304,6 +304,12 @@ config SECCOMP
> > and the task is only allowed to execute a few safe syscalls
> > defined by each seccomp mode.
> >
> > +config RISCV_SBI_V01
> > + bool "SBI v0.1 support"
>
> I don't think presenting this to users as "v0.1" is correct. I'd
> expect that
> to disable probing and
Probing is done in SBI generic code which is necessary to dynamically
figure out the SBI version (v0.1 ..v0.2 or anything else in future).
This doesn't have to do anything with this config option.
> assume the legacy extension always exists, while this
> just allows the legacy extension to be used in a v0.2 style. For
> example: it's
> checking the SBI version, which doesn't exist in v0.1.
>
I am bit confused here. May be we are not on the same page in terms of
terminology. Here is my understanding
v0.1 - All v0.1 calls with v0.1 calling convention.
legacy extensions - representing v0.1 calls as extensions in v0.2
replacement extensions - new extensions defined in v0.2 to replace of
only necessary v0.1 calls. The extension definition and purpose are
defined in
https://github.com/riscv/riscv-sbi-doc/pull/27/commits/3c87fbdacf301a158015b8e57a801c48e30d5738
That's why the unused v0.1 extensions (i.e. CLEAR_IPI, CONSOLE*) are
not defind in replacement extensions.
These replacement extensions must be optional because, we may have
hardware support for these extensions in future. E.g. some hardware may
have tlb flushing as an instruction or can send IPIs directly from S-
mode.
> There should really be two options here: one to allow the legacy
> extension set
> and one to be compatible with SBI v0.1. We can deprecate the v0.1
> support much
> sooner than the legacy extension set.
Why do we need a separate config just to be compatible with SBI v0.1 ?
The calling convention defined in v0.2 is fully backward compatible
with v0.1.
The idea of having a separate config is to help deprecate all
v0.1(=legacy) extensions in future all at once.
> > + default y
> > + help
> > + This config allows kernel to use SBI v0.1 APIs. This will be
> > + deprecated in future once legacy M-mode software are no
> > longer in use.
> > endmenu
> >
> > menu "Boot options"
> > diff --git a/arch/riscv/include/asm/sbi.h
> > b/arch/riscv/include/asm/sbi.h
> > index 906438322932..cc82ae63f8e0 100644
> > --- a/arch/riscv/include/asm/sbi.h
> > +++ b/arch/riscv/include/asm/sbi.h
> > @@ -10,6 +10,7 @@
> >
> > #ifdef CONFIG_RISCV_SBI
> > enum sbi_ext_id {
> > +#ifdef CONFIG_RISCV_SBI_V01
> > SBI_EXT_0_1_SET_TIMER = 0x0,
> > SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
> > SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
> > @@ -19,6 +20,7 @@ enum sbi_ext_id {
> > SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
> > SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
> > SBI_EXT_0_1_SHUTDOWN = 0x8,
> > +#endif
> > SBI_EXT_BASE = 0x10,
> > };
> >
> > diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> > index a47e23c3a2e1..ee710bfe0b0e 100644
> > --- a/arch/riscv/kernel/sbi.c
> > +++ b/arch/riscv/kernel/sbi.c
> > @@ -8,6 +8,14 @@
> > unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
> > EXPORT_SYMBOL(sbi_spec_version);
> >
> > +static void (*__sbi_set_timer)(uint64_t stime);
> > +static int (*__sbi_send_ipi)(const unsigned long *hart_mask);
> > +static int (*__sbi_rfence)(unsigned long extid, unsigned long fid,
> > + const unsigned long *hart_mask,
> > + unsigned long hbase, unsigned long start,
> > + unsigned long size, unsigned long arg4,
> > + unsigned long arg5);
> > +
> > struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> > unsigned long arg1, unsigned long arg2,
> > unsigned long arg3, unsigned long arg4,
> > @@ -52,6 +60,32 @@ static int sbi_err_map_linux_errno(int err)
> > };
> > }
> >
> > +static void __sbi_set_timer_dummy_warn(uint64_t stime_value)
> > +{
> > + pr_warn("Timer extension is not available in SBI v%lu.%lu\n",
> > + sbi_major_version(), sbi_minor_version());
> > +}
> > +
> > +static int __sbi_send_ipi_dummy_warn(const unsigned long
> > *hart_mask)
> > +{
> > + pr_warn("IPI extension is not available in SBI v%lu.%lu\n",
> > + sbi_major_version(), sbi_minor_version());
> > + return 0;
> > +}
> > +
> > +static int __sbi_rfence_dummy_warn(unsigned long extid,
> > + unsigned long fid,
> > + const unsigned long *hart_mask,
> > + unsigned long hbase, unsigned long start,
> > + unsigned long size, unsigned long arg4,
> > + unsigned long arg5)
> > +{
> > + pr_warn("remote fence extension is not available in SBI
> > v%lu.%lu\n",
> > + sbi_major_version(), sbi_minor_version());
> > + return 0;
> > +}
> > +
> > +#ifdef CONFIG_RISCV_SBI_V01
> > /**
> > * sbi_console_putchar() - Writes given character to the console
> > device.
> > * @ch: The data to be written to the console.
> > @@ -80,41 +114,106 @@ int sbi_console_getchar(void)
> > EXPORT_SYMBOL(sbi_console_getchar);
> >
> > /**
> > - * sbi_set_timer() - Program the timer for next timer event.
> > - * @stime_value: The value after which next timer event should
> > fire.
> > + * sbi_shutdown() - Remove all the harts from executing supervisor
> > code.
> > *
> > * Return: None
> > */
> > -void sbi_set_timer(uint64_t stime_value)
> > +void sbi_shutdown(void)
> > {
> > -#if __riscv_xlen == 32
> > - sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
> > - stime_value >> 32, 0, 0, 0, 0);
> > -#else
> > - sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0,
> > 0);
> > -#endif
> > + sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
> > }
> > EXPORT_SYMBOL(sbi_set_timer);
> >
> > /**
> > - * sbi_shutdown() - Remove all the harts from executing supervisor
> > code.
> > + * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
> > *
> > * Return: None
> > */
> > -void sbi_shutdown(void)
> > +void sbi_clear_ipi(void)
> > {
> > - sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
> > + sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
> > }
> > EXPORT_SYMBOL(sbi_shutdown);
> >
> > /**
> > - * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
> > + * sbi_set_timer_v01() - Program the timer for next timer event.
> > + * @stime_value: The value after which next timer event should
> > fire.
> > *
> > * Return: None
> > */
> > -void sbi_clear_ipi(void)
> > +static void __sbi_set_timer_v01(uint64_t stime_value)
> > {
> > - sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
> > +#if __riscv_xlen == 32
> > + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
> > + stime_value >> 32, 0, 0, 0, 0);
> > +#else
> > + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0,
> > 0);
> > +#endif
> > +}
> > +
> > +static int __sbi_send_ipi_v01(const unsigned long *hart_mask)
> > +{
> > + sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
> > + 0, 0, 0, 0, 0);
> > + return 0;
> > +}
> > +
> > +static int __sbi_rfence_v01(unsigned long ext, unsigned long fid,
> > + const unsigned long *hart_mask,
> > + unsigned long hbase, unsigned long start,
> > + unsigned long size, unsigned long arg4,
> > + unsigned long arg5)
> > +{
> > + switch (ext) {
> > + case SBI_EXT_0_1_REMOTE_FENCE_I:
> > + sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0,
> > + (unsigned long)hart_mask, 0, 0, 0, 0, 0);
> > + break;
> > + case SBI_EXT_0_1_REMOTE_SFENCE_VMA:
> > + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
> > + (unsigned long)hart_mask, start, size,
> > + 0, 0, 0);
> > + break;
> > + case SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID:
> > + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
> > + (unsigned long)hart_mask, start, size,
> > + arg4, 0, 0);
> > + break;
> > + default:
> > + pr_err("extid [%lu]not supported in SBI v0.1\n", ext);
> > + }
> > +
> > + return 0;
> > +}
> > +#else
> > +static void __sbi_set_timer_v01(uint64_t stime_value)
> > +{
> > + __sbi_set_timer_dummy_warn(0);
> > +}
> > +static int __sbi_send_ipi_v01(const unsigned long *hart_mask)
> > +{
> > + return __sbi_send_ipi_dummy_warn(NULL);
> > +}
> > +static int __sbi_rfence_v01(unsigned long ext, unsigned long fid,
> > + const unsigned long *hart_mask,
> > + unsigned long hbase, unsigned long start,
> > + unsigned long size, unsigned long arg4,
> > + unsigned long arg5)
> > +{
> > + return __sbi_rfence_dummy_warn(0, 0, 0, 0, 0, 0, 0, 0);
> > +
> > +}
> > +#endif /* CONFIG_RISCV_SBI_V01 */
> > +
> > +/**
> > + * sbi_set_timer() - Program the timer for next timer event.
> > + * @stime_value: The value after which next timer event should
> > fire.
> > + *
> > + * Return: None
> > + */
> > +void sbi_set_timer(uint64_t stime_value)
> > +{
> > + __sbi_set_timer(stime_value);
> > }
> >
> > /**
> > @@ -125,11 +224,11 @@ void sbi_clear_ipi(void)
> > */
> > void sbi_send_ipi(const unsigned long *hart_mask)
> > {
> > - sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
> > - 0, 0, 0, 0, 0);
> > + __sbi_send_ipi(hart_mask);
> > }
> > EXPORT_SYMBOL(sbi_send_ipi);
> >
> > +
> > /**
> > * sbi_remote_fence_i() - Execute FENCE.I instruction on given
> > remote harts.
> > * @hart_mask: A cpu mask containing all the target harts.
> > @@ -138,8 +237,8 @@ EXPORT_SYMBOL(sbi_send_ipi);
> > */
> > void sbi_remote_fence_i(const unsigned long *hart_mask)
> > {
> > - sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned
> > long)hart_mask,
> > - 0, 0, 0, 0, 0);
> > + __sbi_rfence(SBI_EXT_0_1_REMOTE_FENCE_I, 0,
> > + hart_mask, 0, 0, 0, 0, 0);
> > }
> > EXPORT_SYMBOL(sbi_remote_fence_i);
> >
> > @@ -156,8 +255,8 @@ void sbi_remote_sfence_vma(const unsigned long
> > *hart_mask,
> > unsigned long start,
> > unsigned long size)
> > {
> > - sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
> > - (unsigned long)hart_mask, start, size, 0, 0,
> > 0);
> > + __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
> > + hart_mask, 0, start, size, 0, 0);
> > }
> > EXPORT_SYMBOL(sbi_remote_sfence_vma);
> >
> > @@ -177,8 +276,8 @@ void sbi_remote_sfence_vma_asid(const unsigned
> > long *hart_mask,
> > unsigned long size,
> > unsigned long asid)
> > {
> > - sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
> > - (unsigned long)hart_mask, start, size, asid, 0,
> > 0);
> > + __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
> > + hart_mask, 0, start, size, asid, 0);
> > }
> > EXPORT_SYMBOL(sbi_remote_sfence_vma_asid);
> >
> > @@ -253,8 +352,15 @@ int __init sbi_init(void)
> >
> > pr_info("SBI specification v%lu.%lu detected\n",
> > sbi_major_version(), sbi_minor_version());
> > - if (!sbi_spec_is_0_1())
> > +
> > + if (!sbi_spec_is_0_1()) {
> > pr_info("SBI implementation ID=0x%lx Version=0x%lx\n",
> > sbi_get_firmware_id(),
> > sbi_get_firmware_version());
> > + }
> > +
> > + __sbi_set_timer = __sbi_set_timer_v01;
> > + __sbi_send_ipi = __sbi_send_ipi_v01;
> > + __sbi_rfence = __sbi_rfence_v01;
> > +
> > return 0;
> > }
--
Regards,
Atish
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v5 4/4] RISC-V: Implement new SBI v0.2 extensions
2019-11-26 19:04 [PATCH v5 0/4] Add support for SBI v0.2 Atish Patra
` (2 preceding siblings ...)
2019-11-26 19:05 ` [PATCH v5 3/4] RISC-V: Introduce a new config for SBI v0.1 Atish Patra
@ 2019-11-26 19:05 ` Atish Patra
2019-11-29 4:51 ` Anup Patel
2019-12-04 18:52 ` Palmer Dabbelt
2019-12-04 18:56 ` [PATCH v5 0/4] Add support for SBI v0.2 Palmer Dabbelt
4 siblings, 2 replies; 15+ messages in thread
From: Atish Patra @ 2019-11-26 19:05 UTC (permalink / raw)
To: linux-kernel
Cc: Albert Ou, Alexios Zavras, Anup Patel, Mike Rapoport,
Atish Patra, Palmer Dabbelt, Paul Walmsley, linux-riscv,
Thomas Gleixner, Mao Han
Few v0.1 SBI calls are being replaced by new SBI calls that follows
v0.2 calling convention. The specification changes can be found at
riscv/riscv-sbi-doc#27
Implement the replacement extensions and few additional new SBI
function calls that makes way for a better SBI interface in future.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
arch/riscv/include/asm/sbi.h | 35 ++++++
arch/riscv/kernel/sbi.c | 208 +++++++++++++++++++++++++++++++++--
2 files changed, 236 insertions(+), 7 deletions(-)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index cc82ae63f8e0..54ba9eebec11 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -22,6 +22,9 @@ enum sbi_ext_id {
SBI_EXT_0_1_SHUTDOWN = 0x8,
#endif
SBI_EXT_BASE = 0x10,
+ SBI_EXT_TIME = 0x54494D45,
+ SBI_EXT_IPI = 0x735049,
+ SBI_EXT_RFENCE = 0x52464E43,
};
enum sbi_ext_base_fid {
@@ -34,6 +37,24 @@ enum sbi_ext_base_fid {
SBI_BASE_GET_MIMPID,
};
+enum sbi_ext_time_fid {
+ SBI_EXT_TIME_SET_TIMER = 0,
+};
+
+enum sbi_ext_ipi_fid {
+ SBI_EXT_IPI_SEND_IPI = 0,
+};
+
+enum sbi_ext_rfence_fid {
+ SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
+ SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
+ SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
+};
+
#define SBI_SPEC_VERSION_DEFAULT 0x1
#define SBI_SPEC_VERSION_MAJOR_OFFSET 24
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
@@ -74,6 +95,20 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
unsigned long start,
unsigned long size,
unsigned long asid);
+int sbi_remote_hfence_gvma(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size);
+int sbi_remote_hfence_gvma_vmid(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size,
+ unsigned long vmid);
+int sbi_remote_hfence_vvma(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size);
+int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size,
+ unsigned long asid);
int sbi_probe_extension(long ext);
/* Check if current SBI specification version is 0.1 or not */
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index ee710bfe0b0e..af3d5f8d8af7 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -205,6 +205,101 @@ static int __sbi_rfence_v01(unsigned long ext, unsigned long fid,
}
#endif /* CONFIG_RISCV_SBI_V01 */
+static void __sbi_set_timer_v02(uint64_t stime_value)
+{
+#if __riscv_xlen == 32
+ sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value,
+ stime_value >> 32, 0, 0, 0, 0);
+#else
+ sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0,
+ 0, 0, 0, 0);
+#endif
+}
+
+static int __sbi_send_ipi_v02(const unsigned long *hart_mask)
+{
+ unsigned long hmask_val;
+ struct sbiret ret = {0};
+ int result;
+
+ if (!hart_mask)
+ hmask_val = *(cpumask_bits(cpu_online_mask));
+ else
+ hmask_val = *hart_mask;
+
+ ret = sbi_ecall(SBI_EXT_IPI, SBI_EXT_IPI_SEND_IPI, hmask_val,
+ 0, 0, 0, 0, 0);
+ if (ret.error) {
+ pr_err("%s: failed with error [%d]\n", __func__,
+ sbi_err_map_linux_errno(ret.error));
+ result = ret.error;
+ } else
+ result = ret.value;
+
+ return result;
+}
+
+static int __sbi_rfence_v02(unsigned long extid, unsigned long fid,
+ const unsigned long *hart_mask,
+ unsigned long hbase, unsigned long start,
+ unsigned long size, unsigned long arg4,
+ unsigned long arg5)
+{
+ unsigned long hmask_val;
+ struct sbiret ret = {0};
+ int result;
+ unsigned long ext = SBI_EXT_RFENCE;
+
+ if (!hart_mask)
+ hmask_val = *(cpumask_bits(cpu_online_mask));
+ else
+ hmask_val = *hart_mask;
+
+ switch (fid) {
+ case SBI_EXT_RFENCE_REMOTE_FENCE_I:
+ ret = sbi_ecall(ext, fid, hmask_val, 0, 0, 0, 0, 0);
+ break;
+ case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA:
+ ret = sbi_ecall(ext, fid, hmask_val, 0, start,
+ size, 0, 0);
+ break;
+ case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID:
+ ret = sbi_ecall(ext, fid, hmask_val, 0, start,
+ size, arg4, 0);
+ break;
+ /*TODO: Handle non zero hbase cases */
+ case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA:
+ ret = sbi_ecall(ext, fid, hmask_val, 0, start,
+ size, 0, 0);
+ break;
+ case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID:
+ ret = sbi_ecall(ext, fid, hmask_val, 0, start,
+ size, arg4, 0);
+ break;
+ case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA:
+ ret = sbi_ecall(ext, fid, hmask_val, 0, start,
+ size, 0, 0);
+ break;
+ case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID:
+ ret = sbi_ecall(ext, fid, hmask_val, 0, start,
+ size, arg4, 0);
+ break;
+ default:
+ pr_err("unknown function ID [%lu] for SBI extension [%lu]\n",
+ fid, ext);
+ result = -EINVAL;
+ }
+
+ if (ret.error) {
+ pr_err("%s: failed with error [%d]\n", __func__,
+ sbi_err_map_linux_errno(ret.error));
+ result = ret.error;
+ } else
+ result = ret.value;
+
+ return result;
+}
+
/**
* sbi_set_timer() - Program the timer for next timer event.
* @stime_value: The value after which next timer event should fire.
@@ -237,7 +332,7 @@ EXPORT_SYMBOL(sbi_send_ipi);
*/
void sbi_remote_fence_i(const unsigned long *hart_mask)
{
- __sbi_rfence(SBI_EXT_0_1_REMOTE_FENCE_I, 0,
+ __sbi_rfence(SBI_EXT_0_1_REMOTE_FENCE_I, SBI_EXT_RFENCE_REMOTE_FENCE_I,
hart_mask, 0, 0, 0, 0, 0);
}
EXPORT_SYMBOL(sbi_remote_fence_i);
@@ -255,7 +350,8 @@ void sbi_remote_sfence_vma(const unsigned long *hart_mask,
unsigned long start,
unsigned long size)
{
- __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
+ __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA,
+ SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
hart_mask, 0, start, size, 0, 0);
}
EXPORT_SYMBOL(sbi_remote_sfence_vma);
@@ -276,11 +372,93 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
unsigned long size,
unsigned long asid)
{
- __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
+ __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID,
+ SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
hart_mask, 0, start, size, asid, 0);
}
EXPORT_SYMBOL(sbi_remote_sfence_vma_asid);
+/**
+ * sbi_remote_hfence_gvma() - Execute HFENCE.GVMA instructions on given remote
+ * harts for the specified guest physical address range.
+ * @hart_mask: A cpu mask containing all the target harts.
+ * @start: Start of the guest physical address
+ * @size: Total size of the guest physical address range.
+ *
+ * Return: None
+ */
+int sbi_remote_hfence_gvma(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size)
+{
+ return __sbi_rfence(SBI_EXT_RFENCE, SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
+ hart_mask, 0, start, size, 0, 0);
+}
+EXPORT_SYMBOL_GPL(sbi_remote_hfence_gvma);
+
+/**
+ * sbi_remote_hfence_gvma_vmid() - Execute HFENCE.GVMA instructions on given
+ * remote harts for a guest physical address range belonging to a specific VMID.
+ *
+ * @hart_mask: A cpu mask containing all the target harts.
+ * @start: Start of the guest physical address
+ * @size: Total size of the guest physical address range.
+ * @vmid: The value of guest ID (VMID).
+ *
+ * Return: 0 if success, Error otherwise.
+ */
+int sbi_remote_hfence_gvma_vmid(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size,
+ unsigned long vmid)
+{
+ return __sbi_rfence(SBI_EXT_RFENCE,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
+ hart_mask, 0, start, size, vmid, 0);
+}
+EXPORT_SYMBOL(sbi_remote_hfence_gvma_vmid);
+
+/**
+ * sbi_remote_hfence_vvma() - Execute HFENCE.VVMA instructions on given remote
+ * harts for the current guest virtual address range.
+ * @hart_mask: A cpu mask containing all the target harts.
+ * @start: Start of the current guest virtual address
+ * @size: Total size of the current guest virtual address range.
+ *
+ * Return: None
+ */
+int sbi_remote_hfence_vvma(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size)
+{
+ return __sbi_rfence(SBI_EXT_RFENCE, SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
+ hart_mask, 0, start, size, 0, 0);
+}
+EXPORT_SYMBOL(sbi_remote_hfence_vvma);
+
+/**
+ * sbi_remote_hfence_vvma_asid() - Execute HFENCE.VVMA instructions on given
+ * remote harts for current guest virtual address range belonging to a specific
+ * ASID.
+ *
+ * @hart_mask: A cpu mask containing all the target harts.
+ * @start: Start of the current guest virtual address
+ * @size: Total size of the current guest virtual address range.
+ * @asid: The value of address space identifier (ASID).
+ *
+ * Return: None
+ */
+int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size,
+ unsigned long asid)
+{
+ return __sbi_rfence(SBI_EXT_RFENCE,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
+ hart_mask, 0, start, size, asid, 0);
+}
+EXPORT_SYMBOL(sbi_remote_hfence_vvma_asid);
+
/**
* sbi_probe_extension() - Check if an SBI extension ID is supported or not.
* @extid: The extension ID to be probed.
@@ -356,11 +534,27 @@ int __init sbi_init(void)
if (!sbi_spec_is_0_1()) {
pr_info("SBI implementation ID=0x%lx Version=0x%lx\n",
sbi_get_firmware_id(), sbi_get_firmware_version());
+ if (sbi_probe_extension(SBI_EXT_TIME) > 0) {
+ __sbi_set_timer = __sbi_set_timer_v02;
+ pr_info("SBI v0.2 TIME extension detected\n");
+ } else
+ __sbi_set_timer = __sbi_set_timer_dummy_warn;
+ if (sbi_probe_extension(SBI_EXT_IPI) > 0) {
+ __sbi_send_ipi = __sbi_send_ipi_v02;
+ pr_info("SBI v0.2 IPI extension detected\n");
+ } else
+ __sbi_send_ipi = __sbi_send_ipi_dummy_warn;
+ if (sbi_probe_extension(SBI_EXT_RFENCE) > 0) {
+ __sbi_rfence = __sbi_rfence_v02;
+ pr_info("SBI v0.2 RFENCE extension detected\n");
+ } else
+ __sbi_rfence = __sbi_rfence_dummy_warn;
+
+ } else {
+ __sbi_set_timer = __sbi_set_timer_v01;
+ __sbi_send_ipi = __sbi_send_ipi_v01;
+ __sbi_rfence = __sbi_rfence_v01;
}
- __sbi_set_timer = __sbi_set_timer_v01;
- __sbi_send_ipi = __sbi_send_ipi_v01;
- __sbi_rfence = __sbi_rfence_v01;
-
return 0;
}
--
2.23.0
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v5 4/4] RISC-V: Implement new SBI v0.2 extensions
2019-11-26 19:05 ` [PATCH v5 4/4] RISC-V: Implement new SBI v0.2 extensions Atish Patra
@ 2019-11-29 4:51 ` Anup Patel
2019-11-29 4:57 ` Anup Patel
2019-12-04 18:52 ` Palmer Dabbelt
1 sibling, 1 reply; 15+ messages in thread
From: Anup Patel @ 2019-11-29 4:51 UTC (permalink / raw)
To: Atish Patra
Cc: Albert Ou, linux-kernel@vger.kernel.org List, Mike Rapoport,
Alexios Zavras, Palmer Dabbelt, Paul Walmsley, linux-riscv,
Thomas Gleixner, Mao Han
Hi Atish,
Found few bugs while playing with this patch.
See below ....
On Wed, Nov 27, 2019 at 12:35 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> Few v0.1 SBI calls are being replaced by new SBI calls that follows
> v0.2 calling convention. The specification changes can be found at
>
> riscv/riscv-sbi-doc#27
>
> Implement the replacement extensions and few additional new SBI
> function calls that makes way for a better SBI interface in future.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> arch/riscv/include/asm/sbi.h | 35 ++++++
> arch/riscv/kernel/sbi.c | 208 +++++++++++++++++++++++++++++++++--
> 2 files changed, 236 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index cc82ae63f8e0..54ba9eebec11 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -22,6 +22,9 @@ enum sbi_ext_id {
> SBI_EXT_0_1_SHUTDOWN = 0x8,
> #endif
> SBI_EXT_BASE = 0x10,
> + SBI_EXT_TIME = 0x54494D45,
> + SBI_EXT_IPI = 0x735049,
> + SBI_EXT_RFENCE = 0x52464E43,
> };
>
> enum sbi_ext_base_fid {
> @@ -34,6 +37,24 @@ enum sbi_ext_base_fid {
> SBI_BASE_GET_MIMPID,
> };
>
> +enum sbi_ext_time_fid {
> + SBI_EXT_TIME_SET_TIMER = 0,
> +};
> +
> +enum sbi_ext_ipi_fid {
> + SBI_EXT_IPI_SEND_IPI = 0,
> +};
> +
> +enum sbi_ext_rfence_fid {
> + SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
> + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
> + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
> + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
> + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
> +};
> +
> #define SBI_SPEC_VERSION_DEFAULT 0x1
> #define SBI_SPEC_VERSION_MAJOR_OFFSET 24
> #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
> @@ -74,6 +95,20 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> unsigned long start,
> unsigned long size,
> unsigned long asid);
> +int sbi_remote_hfence_gvma(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size);
> +int sbi_remote_hfence_gvma_vmid(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size,
> + unsigned long vmid);
> +int sbi_remote_hfence_vvma(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size);
> +int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size,
> + unsigned long asid);
> int sbi_probe_extension(long ext);
>
> /* Check if current SBI specification version is 0.1 or not */
> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> index ee710bfe0b0e..af3d5f8d8af7 100644
> --- a/arch/riscv/kernel/sbi.c
> +++ b/arch/riscv/kernel/sbi.c
> @@ -205,6 +205,101 @@ static int __sbi_rfence_v01(unsigned long ext, unsigned long fid,
> }
> #endif /* CONFIG_RISCV_SBI_V01 */
>
> +static void __sbi_set_timer_v02(uint64_t stime_value)
> +{
> +#if __riscv_xlen == 32
> + sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value,
> + stime_value >> 32, 0, 0, 0, 0);
> +#else
> + sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0,
> + 0, 0, 0, 0);
> +#endif
> +}
> +
> +static int __sbi_send_ipi_v02(const unsigned long *hart_mask)
> +{
> + unsigned long hmask_val;
> + struct sbiret ret = {0};
> + int result;
> +
> + if (!hart_mask)
> + hmask_val = *(cpumask_bits(cpu_online_mask));
> + else
> + hmask_val = *hart_mask;
> +
> + ret = sbi_ecall(SBI_EXT_IPI, SBI_EXT_IPI_SEND_IPI, hmask_val,
> + 0, 0, 0, 0, 0);
> + if (ret.error) {
> + pr_err("%s: failed with error [%d]\n", __func__,
> + sbi_err_map_linux_errno(ret.error));
> + result = ret.error;
> + } else
> + result = ret.value;
> +
> + return result;
> +}
> +
> +static int __sbi_rfence_v02(unsigned long extid, unsigned long fid,
> + const unsigned long *hart_mask,
> + unsigned long hbase, unsigned long start,
> + unsigned long size, unsigned long arg4,
> + unsigned long arg5)
> +{
> + unsigned long hmask_val;
> + struct sbiret ret = {0};
> + int result;
> + unsigned long ext = SBI_EXT_RFENCE;
> +
> + if (!hart_mask)
> + hmask_val = *(cpumask_bits(cpu_online_mask));
> + else
> + hmask_val = *hart_mask;
> +
> + switch (fid) {
> + case SBI_EXT_RFENCE_REMOTE_FENCE_I:
> + ret = sbi_ecall(ext, fid, hmask_val, 0, 0, 0, 0, 0);
> + break;
> + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA:
> + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> + size, 0, 0);
> + break;
> + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID:
> + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> + size, arg4, 0);
> + break;
> + /*TODO: Handle non zero hbase cases */
> + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA:
> + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> + size, 0, 0);
> + break;
> + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID:
> + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> + size, arg4, 0);
> + break;
> + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA:
> + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> + size, 0, 0);
> + break;
> + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID:
> + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> + size, arg4, 0);
> + break;
> + default:
> + pr_err("unknown function ID [%lu] for SBI extension [%lu]\n",
> + fid, ext);
> + result = -EINVAL;
> + }
> +
> + if (ret.error) {
> + pr_err("%s: failed with error [%d]\n", __func__,
> + sbi_err_map_linux_errno(ret.error));
> + result = ret.error;
> + } else
> + result = ret.value;
> +
> + return result;
> +}
> +
> /**
> * sbi_set_timer() - Program the timer for next timer event.
> * @stime_value: The value after which next timer event should fire.
> @@ -237,7 +332,7 @@ EXPORT_SYMBOL(sbi_send_ipi);
> */
> void sbi_remote_fence_i(const unsigned long *hart_mask)
> {
> - __sbi_rfence(SBI_EXT_0_1_REMOTE_FENCE_I, 0,
> + __sbi_rfence(SBI_EXT_0_1_REMOTE_FENCE_I, SBI_EXT_RFENCE_REMOTE_FENCE_I,
> hart_mask, 0, 0, 0, 0, 0);
> }
> EXPORT_SYMBOL(sbi_remote_fence_i);
> @@ -255,7 +350,8 @@ void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> unsigned long start,
> unsigned long size)
> {
> - __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
> + __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA,
> + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
> hart_mask, 0, start, size, 0, 0);
> }
> EXPORT_SYMBOL(sbi_remote_sfence_vma);
> @@ -276,11 +372,93 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> unsigned long size,
> unsigned long asid)
> {
> - __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
> + __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID,
> + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
> hart_mask, 0, start, size, asid, 0);
> }
> EXPORT_SYMBOL(sbi_remote_sfence_vma_asid);
>
> +/**
> + * sbi_remote_hfence_gvma() - Execute HFENCE.GVMA instructions on given remote
> + * harts for the specified guest physical address range.
> + * @hart_mask: A cpu mask containing all the target harts.
> + * @start: Start of the guest physical address
> + * @size: Total size of the guest physical address range.
> + *
> + * Return: None
> + */
> +int sbi_remote_hfence_gvma(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size)
> +{
> + return __sbi_rfence(SBI_EXT_RFENCE, SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> + hart_mask, 0, start, size, 0, 0);
> +}
> +EXPORT_SYMBOL_GPL(sbi_remote_hfence_gvma);
> +
> +/**
> + * sbi_remote_hfence_gvma_vmid() - Execute HFENCE.GVMA instructions on given
> + * remote harts for a guest physical address range belonging to a specific VMID.
> + *
> + * @hart_mask: A cpu mask containing all the target harts.
> + * @start: Start of the guest physical address
> + * @size: Total size of the guest physical address range.
> + * @vmid: The value of guest ID (VMID).
> + *
> + * Return: 0 if success, Error otherwise.
> + */
> +int sbi_remote_hfence_gvma_vmid(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size,
> + unsigned long vmid)
> +{
> + return __sbi_rfence(SBI_EXT_RFENCE,
> + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
> + hart_mask, 0, start, size, vmid, 0);
> +}
> +EXPORT_SYMBOL(sbi_remote_hfence_gvma_vmid);
> +
> +/**
> + * sbi_remote_hfence_vvma() - Execute HFENCE.VVMA instructions on given remote
> + * harts for the current guest virtual address range.
> + * @hart_mask: A cpu mask containing all the target harts.
> + * @start: Start of the current guest virtual address
> + * @size: Total size of the current guest virtual address range.
> + *
> + * Return: None
> + */
> +int sbi_remote_hfence_vvma(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size)
> +{
> + return __sbi_rfence(SBI_EXT_RFENCE, SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> + hart_mask, 0, start, size, 0, 0);
> +}
> +EXPORT_SYMBOL(sbi_remote_hfence_vvma);
> +
> +/**
> + * sbi_remote_hfence_vvma_asid() - Execute HFENCE.VVMA instructions on given
> + * remote harts for current guest virtual address range belonging to a specific
> + * ASID.
> + *
> + * @hart_mask: A cpu mask containing all the target harts.
> + * @start: Start of the current guest virtual address
> + * @size: Total size of the current guest virtual address range.
> + * @asid: The value of address space identifier (ASID).
> + *
> + * Return: None
> + */
> +int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size,
> + unsigned long asid)
> +{
> + return __sbi_rfence(SBI_EXT_RFENCE,
> + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
> + hart_mask, 0, start, size, asid, 0);
> +}
> +EXPORT_SYMBOL(sbi_remote_hfence_vvma_asid);
> +
> /**
> * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
> * @extid: The extension ID to be probed.
> @@ -356,11 +534,27 @@ int __init sbi_init(void)
> if (!sbi_spec_is_0_1()) {
> pr_info("SBI implementation ID=0x%lx Version=0x%lx\n",
> sbi_get_firmware_id(), sbi_get_firmware_version());
> + if (sbi_probe_extension(SBI_EXT_TIME) > 0) {
> + __sbi_set_timer = __sbi_set_timer_v02;
> + pr_info("SBI v0.2 TIME extension detected\n");
> + } else
> + __sbi_set_timer = __sbi_set_timer_dummy_warn;
This should be:
#if IS_ENABLED(RISCV_SBI_V01)
__sbi_rfence = __sbi_set_timer_v01;
#else
__sbi_rfence = __sbi_set_timer_dummy_warn;
#endif
> + if (sbi_probe_extension(SBI_EXT_IPI) > 0) {
> + __sbi_send_ipi = __sbi_send_ipi_v02;
> + pr_info("SBI v0.2 IPI extension detected\n");
> + } else
> + __sbi_send_ipi = __sbi_send_ipi_dummy_warn;
This should be:
#if IS_ENABLED(RISCV_SBI_V01)
__sbi_rfence = __sbi_ipi_v01;
#else
__sbi_rfence = __sbi_send_ipi_dummy_warn;
#endif
> + if (sbi_probe_extension(SBI_EXT_RFENCE) > 0) {
> + __sbi_rfence = __sbi_rfence_v02;
> + pr_info("SBI v0.2 RFENCE extension detected\n");
> + } else
> + __sbi_rfence = __sbi_rfence_dummy_warn;
This should be:
#if IS_ENABLED(RISCV_SBI_V01)
__sbi_rfence = __sbi_rfence_v01;
#else
__sbi_rfence = __sbi_rfence_dummy_warn;
#endif
> +
> + } else {
> + __sbi_set_timer = __sbi_set_timer_v01;
> + __sbi_send_ipi = __sbi_send_ipi_v01;
> + __sbi_rfence = __sbi_rfence_v01;
This should be:
#if IS_ENABLED(RISCV_SBI_V01)
__sbi_set_timer = __sbi_set_timer_v01;
__sbi_send_ipi = __sbi_send_ipi_v01;
__sbi_rfence = __sbi_rfence_v01;
#else
__sbi_set_timer = __sbi_set_timer_dummy_warn;
__sbi_send_ipi = __sbi_send_ipi_dummy_warn;
__sbi_rfence = __sbi_rfence_dummy_warn;
#endif
> }
>
> - __sbi_set_timer = __sbi_set_timer_v01;
> - __sbi_send_ipi = __sbi_send_ipi_v01;
> - __sbi_rfence = __sbi_rfence_v01;
> -
> return 0;
> }
> --
> 2.23.0
>
Regards,
Anup
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v5 4/4] RISC-V: Implement new SBI v0.2 extensions
2019-11-29 4:51 ` Anup Patel
@ 2019-11-29 4:57 ` Anup Patel
2019-12-04 21:10 ` Atish Patra
0 siblings, 1 reply; 15+ messages in thread
From: Anup Patel @ 2019-11-29 4:57 UTC (permalink / raw)
To: Atish Patra
Cc: Albert Ou, linux-kernel@vger.kernel.org List, Mike Rapoport,
Alexios Zavras, Palmer Dabbelt, Paul Walmsley, linux-riscv,
Thomas Gleixner, Mao Han
On Fri, Nov 29, 2019 at 10:21 AM Anup Patel <anup@brainfault.org> wrote:
>
> Hi Atish,
>
> Found few bugs while playing with this patch.
>
> See below ....
>
> On Wed, Nov 27, 2019 at 12:35 AM Atish Patra <atish.patra@wdc.com> wrote:
> >
> > Few v0.1 SBI calls are being replaced by new SBI calls that follows
> > v0.2 calling convention. The specification changes can be found at
> >
> > riscv/riscv-sbi-doc#27
> >
> > Implement the replacement extensions and few additional new SBI
> > function calls that makes way for a better SBI interface in future.
> >
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > Reviewed-by: Anup Patel <anup@brainfault.org>
> > ---
> > arch/riscv/include/asm/sbi.h | 35 ++++++
> > arch/riscv/kernel/sbi.c | 208 +++++++++++++++++++++++++++++++++--
> > 2 files changed, 236 insertions(+), 7 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> > index cc82ae63f8e0..54ba9eebec11 100644
> > --- a/arch/riscv/include/asm/sbi.h
> > +++ b/arch/riscv/include/asm/sbi.h
> > @@ -22,6 +22,9 @@ enum sbi_ext_id {
> > SBI_EXT_0_1_SHUTDOWN = 0x8,
> > #endif
> > SBI_EXT_BASE = 0x10,
> > + SBI_EXT_TIME = 0x54494D45,
> > + SBI_EXT_IPI = 0x735049,
> > + SBI_EXT_RFENCE = 0x52464E43,
> > };
> >
> > enum sbi_ext_base_fid {
> > @@ -34,6 +37,24 @@ enum sbi_ext_base_fid {
> > SBI_BASE_GET_MIMPID,
> > };
> >
> > +enum sbi_ext_time_fid {
> > + SBI_EXT_TIME_SET_TIMER = 0,
> > +};
> > +
> > +enum sbi_ext_ipi_fid {
> > + SBI_EXT_IPI_SEND_IPI = 0,
> > +};
> > +
> > +enum sbi_ext_rfence_fid {
> > + SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
> > + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
> > + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
> > + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> > + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
> > + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> > + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
> > +};
> > +
> > #define SBI_SPEC_VERSION_DEFAULT 0x1
> > #define SBI_SPEC_VERSION_MAJOR_OFFSET 24
> > #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
> > @@ -74,6 +95,20 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> > unsigned long start,
> > unsigned long size,
> > unsigned long asid);
> > +int sbi_remote_hfence_gvma(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size);
> > +int sbi_remote_hfence_gvma_vmid(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size,
> > + unsigned long vmid);
> > +int sbi_remote_hfence_vvma(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size);
> > +int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size,
> > + unsigned long asid);
> > int sbi_probe_extension(long ext);
> >
> > /* Check if current SBI specification version is 0.1 or not */
> > diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> > index ee710bfe0b0e..af3d5f8d8af7 100644
> > --- a/arch/riscv/kernel/sbi.c
> > +++ b/arch/riscv/kernel/sbi.c
> > @@ -205,6 +205,101 @@ static int __sbi_rfence_v01(unsigned long ext, unsigned long fid,
> > }
> > #endif /* CONFIG_RISCV_SBI_V01 */
> >
> > +static void __sbi_set_timer_v02(uint64_t stime_value)
> > +{
> > +#if __riscv_xlen == 32
> > + sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value,
> > + stime_value >> 32, 0, 0, 0, 0);
> > +#else
> > + sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0,
> > + 0, 0, 0, 0);
> > +#endif
> > +}
> > +
> > +static int __sbi_send_ipi_v02(const unsigned long *hart_mask)
> > +{
> > + unsigned long hmask_val;
> > + struct sbiret ret = {0};
> > + int result;
> > +
> > + if (!hart_mask)
> > + hmask_val = *(cpumask_bits(cpu_online_mask));
> > + else
> > + hmask_val = *hart_mask;
> > +
> > + ret = sbi_ecall(SBI_EXT_IPI, SBI_EXT_IPI_SEND_IPI, hmask_val,
> > + 0, 0, 0, 0, 0);
> > + if (ret.error) {
> > + pr_err("%s: failed with error [%d]\n", __func__,
> > + sbi_err_map_linux_errno(ret.error));
> > + result = ret.error;
> > + } else
> > + result = ret.value;
> > +
> > + return result;
> > +}
> > +
> > +static int __sbi_rfence_v02(unsigned long extid, unsigned long fid,
> > + const unsigned long *hart_mask,
> > + unsigned long hbase, unsigned long start,
> > + unsigned long size, unsigned long arg4,
> > + unsigned long arg5)
> > +{
> > + unsigned long hmask_val;
> > + struct sbiret ret = {0};
> > + int result;
> > + unsigned long ext = SBI_EXT_RFENCE;
> > +
> > + if (!hart_mask)
> > + hmask_val = *(cpumask_bits(cpu_online_mask));
> > + else
> > + hmask_val = *hart_mask;
> > +
> > + switch (fid) {
> > + case SBI_EXT_RFENCE_REMOTE_FENCE_I:
> > + ret = sbi_ecall(ext, fid, hmask_val, 0, 0, 0, 0, 0);
> > + break;
> > + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA:
> > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > + size, 0, 0);
> > + break;
> > + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID:
> > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > + size, arg4, 0);
> > + break;
> > + /*TODO: Handle non zero hbase cases */
> > + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA:
> > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > + size, 0, 0);
> > + break;
> > + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID:
> > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > + size, arg4, 0);
> > + break;
> > + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA:
> > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > + size, 0, 0);
> > + break;
> > + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID:
> > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > + size, arg4, 0);
> > + break;
> > + default:
> > + pr_err("unknown function ID [%lu] for SBI extension [%lu]\n",
> > + fid, ext);
> > + result = -EINVAL;
> > + }
> > +
> > + if (ret.error) {
> > + pr_err("%s: failed with error [%d]\n", __func__,
> > + sbi_err_map_linux_errno(ret.error));
> > + result = ret.error;
> > + } else
> > + result = ret.value;
> > +
> > + return result;
> > +}
> > +
> > /**
> > * sbi_set_timer() - Program the timer for next timer event.
> > * @stime_value: The value after which next timer event should fire.
> > @@ -237,7 +332,7 @@ EXPORT_SYMBOL(sbi_send_ipi);
> > */
> > void sbi_remote_fence_i(const unsigned long *hart_mask)
> > {
> > - __sbi_rfence(SBI_EXT_0_1_REMOTE_FENCE_I, 0,
> > + __sbi_rfence(SBI_EXT_0_1_REMOTE_FENCE_I, SBI_EXT_RFENCE_REMOTE_FENCE_I,
> > hart_mask, 0, 0, 0, 0, 0);
> > }
> > EXPORT_SYMBOL(sbi_remote_fence_i);
> > @@ -255,7 +350,8 @@ void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> > unsigned long start,
> > unsigned long size)
> > {
> > - __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
> > + __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA,
> > + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
> > hart_mask, 0, start, size, 0, 0);
> > }
> > EXPORT_SYMBOL(sbi_remote_sfence_vma);
> > @@ -276,11 +372,93 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> > unsigned long size,
> > unsigned long asid)
> > {
> > - __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
> > + __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID,
> > + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
> > hart_mask, 0, start, size, asid, 0);
> > }
> > EXPORT_SYMBOL(sbi_remote_sfence_vma_asid);
> >
> > +/**
> > + * sbi_remote_hfence_gvma() - Execute HFENCE.GVMA instructions on given remote
> > + * harts for the specified guest physical address range.
> > + * @hart_mask: A cpu mask containing all the target harts.
> > + * @start: Start of the guest physical address
> > + * @size: Total size of the guest physical address range.
> > + *
> > + * Return: None
> > + */
> > +int sbi_remote_hfence_gvma(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size)
> > +{
> > + return __sbi_rfence(SBI_EXT_RFENCE, SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> > + hart_mask, 0, start, size, 0, 0);
> > +}
> > +EXPORT_SYMBOL_GPL(sbi_remote_hfence_gvma);
> > +
> > +/**
> > + * sbi_remote_hfence_gvma_vmid() - Execute HFENCE.GVMA instructions on given
> > + * remote harts for a guest physical address range belonging to a specific VMID.
> > + *
> > + * @hart_mask: A cpu mask containing all the target harts.
> > + * @start: Start of the guest physical address
> > + * @size: Total size of the guest physical address range.
> > + * @vmid: The value of guest ID (VMID).
> > + *
> > + * Return: 0 if success, Error otherwise.
> > + */
> > +int sbi_remote_hfence_gvma_vmid(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size,
> > + unsigned long vmid)
> > +{
> > + return __sbi_rfence(SBI_EXT_RFENCE,
> > + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
> > + hart_mask, 0, start, size, vmid, 0);
> > +}
> > +EXPORT_SYMBOL(sbi_remote_hfence_gvma_vmid);
> > +
> > +/**
> > + * sbi_remote_hfence_vvma() - Execute HFENCE.VVMA instructions on given remote
> > + * harts for the current guest virtual address range.
> > + * @hart_mask: A cpu mask containing all the target harts.
> > + * @start: Start of the current guest virtual address
> > + * @size: Total size of the current guest virtual address range.
> > + *
> > + * Return: None
> > + */
> > +int sbi_remote_hfence_vvma(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size)
> > +{
> > + return __sbi_rfence(SBI_EXT_RFENCE, SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> > + hart_mask, 0, start, size, 0, 0);
> > +}
> > +EXPORT_SYMBOL(sbi_remote_hfence_vvma);
> > +
> > +/**
> > + * sbi_remote_hfence_vvma_asid() - Execute HFENCE.VVMA instructions on given
> > + * remote harts for current guest virtual address range belonging to a specific
> > + * ASID.
> > + *
> > + * @hart_mask: A cpu mask containing all the target harts.
> > + * @start: Start of the current guest virtual address
> > + * @size: Total size of the current guest virtual address range.
> > + * @asid: The value of address space identifier (ASID).
> > + *
> > + * Return: None
> > + */
> > +int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size,
> > + unsigned long asid)
> > +{
> > + return __sbi_rfence(SBI_EXT_RFENCE,
> > + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
> > + hart_mask, 0, start, size, asid, 0);
> > +}
> > +EXPORT_SYMBOL(sbi_remote_hfence_vvma_asid);
> > +
> > /**
> > * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
> > * @extid: The extension ID to be probed.
> > @@ -356,11 +534,27 @@ int __init sbi_init(void)
> > if (!sbi_spec_is_0_1()) {
> > pr_info("SBI implementation ID=0x%lx Version=0x%lx\n",
> > sbi_get_firmware_id(), sbi_get_firmware_version());
> > + if (sbi_probe_extension(SBI_EXT_TIME) > 0) {
> > + __sbi_set_timer = __sbi_set_timer_v02;
> > + pr_info("SBI v0.2 TIME extension detected\n");
> > + } else
> > + __sbi_set_timer = __sbi_set_timer_dummy_warn;
> This should be:
>
> #if IS_ENABLED(RISCV_SBI_V01)
> __sbi_rfence = __sbi_set_timer_v01;
> #else
> __sbi_rfence = __sbi_set_timer_dummy_warn;
> #endif
Instead of this, just do the following:
__sbi_rfence = __sbi_set_timer_v01;
>
> > + if (sbi_probe_extension(SBI_EXT_IPI) > 0) {
> > + __sbi_send_ipi = __sbi_send_ipi_v02;
> > + pr_info("SBI v0.2 IPI extension detected\n");
> > + } else
> > + __sbi_send_ipi = __sbi_send_ipi_dummy_warn;
> This should be:
>
> #if IS_ENABLED(RISCV_SBI_V01)
> __sbi_rfence = __sbi_ipi_v01;
> #else
> __sbi_rfence = __sbi_send_ipi_dummy_warn;
> #endif
Instead of this, just do the following:
__sbi_rfence = __sbi_ipi_v01;
>
> > + if (sbi_probe_extension(SBI_EXT_RFENCE) > 0) {
> > + __sbi_rfence = __sbi_rfence_v02;
> > + pr_info("SBI v0.2 RFENCE extension detected\n");
> > + } else
> > + __sbi_rfence = __sbi_rfence_dummy_warn;
> This should be:
>
> #if IS_ENABLED(RISCV_SBI_V01)
> __sbi_rfence = __sbi_rfence_v01;
> #else
> __sbi_rfence = __sbi_rfence_dummy_warn;
> #endif
Instead of this, just do the following:
__sbi_rfence = __sbi_rfence_v01;
>
> > +
> > + } else {
> > + __sbi_set_timer = __sbi_set_timer_v01;
> > + __sbi_send_ipi = __sbi_send_ipi_v01;
> > + __sbi_rfence = __sbi_rfence_v01;
>
> This should be:
>
> #if IS_ENABLED(RISCV_SBI_V01)
> __sbi_set_timer = __sbi_set_timer_v01;
> __sbi_send_ipi = __sbi_send_ipi_v01;
> __sbi_rfence = __sbi_rfence_v01;
> #else
> __sbi_set_timer = __sbi_set_timer_dummy_warn;
> __sbi_send_ipi = __sbi_send_ipi_dummy_warn;
> __sbi_rfence = __sbi_rfence_dummy_warn;
> #endif
This is not required.
> > }
> >
> > - __sbi_set_timer = __sbi_set_timer_v01;
> > - __sbi_send_ipi = __sbi_send_ipi_v01;
> > - __sbi_rfence = __sbi_rfence_v01;
> > -
> > return 0;
> > }
> > --
> > 2.23.0
> >
>
> Regards,
> Anup
Regards,
Anup
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linux-riscv@lists.infradead.org
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v5 4/4] RISC-V: Implement new SBI v0.2 extensions
2019-11-29 4:57 ` Anup Patel
@ 2019-12-04 21:10 ` Atish Patra
0 siblings, 0 replies; 15+ messages in thread
From: Atish Patra @ 2019-12-04 21:10 UTC (permalink / raw)
To: anup
Cc: aou, linux-kernel, rppt, alexios.zavras, palmer, paul.walmsley,
linux-riscv, tglx, han_mao
On Fri, 2019-11-29 at 10:27 +0530, Anup Patel wrote:
> On Fri, Nov 29, 2019 at 10:21 AM Anup Patel <anup@brainfault.org>
> wrote:
> > Hi Atish,
> >
> > Found few bugs while playing with this patch.
> >
> > See below ....
> >
> > On Wed, Nov 27, 2019 at 12:35 AM Atish Patra <atish.patra@wdc.com>
> > wrote:
> > > Few v0.1 SBI calls are being replaced by new SBI calls that
> > > follows
> > > v0.2 calling convention. The specification changes can be found
> > > at
> > >
> > > riscv/riscv-sbi-doc#27
> > >
> > > Implement the replacement extensions and few additional new SBI
> > > function calls that makes way for a better SBI interface in
> > > future.
> > >
> > > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > > Reviewed-by: Anup Patel <anup@brainfault.org>
> > > ---
> > > arch/riscv/include/asm/sbi.h | 35 ++++++
> > > arch/riscv/kernel/sbi.c | 208
> > > +++++++++++++++++++++++++++++++++--
> > > 2 files changed, 236 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/arch/riscv/include/asm/sbi.h
> > > b/arch/riscv/include/asm/sbi.h
> > > index cc82ae63f8e0..54ba9eebec11 100644
> > > --- a/arch/riscv/include/asm/sbi.h
> > > +++ b/arch/riscv/include/asm/sbi.h
> > > @@ -22,6 +22,9 @@ enum sbi_ext_id {
> > > SBI_EXT_0_1_SHUTDOWN = 0x8,
> > > #endif
> > > SBI_EXT_BASE = 0x10,
> > > + SBI_EXT_TIME = 0x54494D45,
> > > + SBI_EXT_IPI = 0x735049,
> > > + SBI_EXT_RFENCE = 0x52464E43,
> > > };
> > >
> > > enum sbi_ext_base_fid {
> > > @@ -34,6 +37,24 @@ enum sbi_ext_base_fid {
> > > SBI_BASE_GET_MIMPID,
> > > };
> > >
> > > +enum sbi_ext_time_fid {
> > > + SBI_EXT_TIME_SET_TIMER = 0,
> > > +};
> > > +
> > > +enum sbi_ext_ipi_fid {
> > > + SBI_EXT_IPI_SEND_IPI = 0,
> > > +};
> > > +
> > > +enum sbi_ext_rfence_fid {
> > > + SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
> > > + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
> > > + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
> > > + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> > > + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
> > > + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> > > + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
> > > +};
> > > +
> > > #define SBI_SPEC_VERSION_DEFAULT 0x1
> > > #define SBI_SPEC_VERSION_MAJOR_OFFSET 24
> > > #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
> > > @@ -74,6 +95,20 @@ void sbi_remote_sfence_vma_asid(const unsigned
> > > long *hart_mask,
> > > unsigned long start,
> > > unsigned long size,
> > > unsigned long asid);
> > > +int sbi_remote_hfence_gvma(const unsigned long *hart_mask,
> > > + unsigned long start,
> > > + unsigned long size);
> > > +int sbi_remote_hfence_gvma_vmid(const unsigned long *hart_mask,
> > > + unsigned long start,
> > > + unsigned long size,
> > > + unsigned long vmid);
> > > +int sbi_remote_hfence_vvma(const unsigned long *hart_mask,
> > > + unsigned long start,
> > > + unsigned long size);
> > > +int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
> > > + unsigned long start,
> > > + unsigned long size,
> > > + unsigned long asid);
> > > int sbi_probe_extension(long ext);
> > >
> > > /* Check if current SBI specification version is 0.1 or not */
> > > diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> > > index ee710bfe0b0e..af3d5f8d8af7 100644
> > > --- a/arch/riscv/kernel/sbi.c
> > > +++ b/arch/riscv/kernel/sbi.c
> > > @@ -205,6 +205,101 @@ static int __sbi_rfence_v01(unsigned long
> > > ext, unsigned long fid,
> > > }
> > > #endif /* CONFIG_RISCV_SBI_V01 */
> > >
> > > +static void __sbi_set_timer_v02(uint64_t stime_value)
> > > +{
> > > +#if __riscv_xlen == 32
> > > + sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER,
> > > stime_value,
> > > + stime_value >> 32, 0, 0, 0, 0);
> > > +#else
> > > + sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER,
> > > stime_value, 0,
> > > + 0, 0, 0, 0);
> > > +#endif
> > > +}
> > > +
> > > +static int __sbi_send_ipi_v02(const unsigned long *hart_mask)
> > > +{
> > > + unsigned long hmask_val;
> > > + struct sbiret ret = {0};
> > > + int result;
> > > +
> > > + if (!hart_mask)
> > > + hmask_val = *(cpumask_bits(cpu_online_mask));
> > > + else
> > > + hmask_val = *hart_mask;
> > > +
> > > + ret = sbi_ecall(SBI_EXT_IPI, SBI_EXT_IPI_SEND_IPI,
> > > hmask_val,
> > > + 0, 0, 0, 0, 0);
> > > + if (ret.error) {
> > > + pr_err("%s: failed with error [%d]\n", __func__,
> > > + sbi_err_map_linux_errno(ret.error));
> > > + result = ret.error;
> > > + } else
> > > + result = ret.value;
> > > +
> > > + return result;
> > > +}
> > > +
> > > +static int __sbi_rfence_v02(unsigned long extid, unsigned long
> > > fid,
> > > + const unsigned long *hart_mask,
> > > + unsigned long hbase, unsigned long
> > > start,
> > > + unsigned long size, unsigned long
> > > arg4,
> > > + unsigned long arg5)
> > > +{
> > > + unsigned long hmask_val;
> > > + struct sbiret ret = {0};
> > > + int result;
> > > + unsigned long ext = SBI_EXT_RFENCE;
> > > +
> > > + if (!hart_mask)
> > > + hmask_val = *(cpumask_bits(cpu_online_mask));
> > > + else
> > > + hmask_val = *hart_mask;
> > > +
> > > + switch (fid) {
> > > + case SBI_EXT_RFENCE_REMOTE_FENCE_I:
> > > + ret = sbi_ecall(ext, fid, hmask_val, 0, 0, 0, 0,
> > > 0);
> > > + break;
> > > + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA:
> > > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > > + size, 0, 0);
> > > + break;
> > > + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID:
> > > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > > + size, arg4, 0);
> > > + break;
> > > + /*TODO: Handle non zero hbase cases */
> > > + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA:
> > > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > > + size, 0, 0);
> > > + break;
> > > + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID:
> > > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > > + size, arg4, 0);
> > > + break;
> > > + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA:
> > > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > > + size, 0, 0);
> > > + break;
> > > + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID:
> > > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > > + size, arg4, 0);
> > > + break;
> > > + default:
> > > + pr_err("unknown function ID [%lu] for SBI
> > > extension [%lu]\n",
> > > + fid, ext);
> > > + result = -EINVAL;
> > > + }
> > > +
> > > + if (ret.error) {
> > > + pr_err("%s: failed with error [%d]\n", __func__,
> > > + sbi_err_map_linux_errno(ret.error));
> > > + result = ret.error;
> > > + } else
> > > + result = ret.value;
> > > +
> > > + return result;
> > > +}
> > > +
> > > /**
> > > * sbi_set_timer() - Program the timer for next timer event.
> > > * @stime_value: The value after which next timer event should
> > > fire.
> > > @@ -237,7 +332,7 @@ EXPORT_SYMBOL(sbi_send_ipi);
> > > */
> > > void sbi_remote_fence_i(const unsigned long *hart_mask)
> > > {
> > > - __sbi_rfence(SBI_EXT_0_1_REMOTE_FENCE_I, 0,
> > > + __sbi_rfence(SBI_EXT_0_1_REMOTE_FENCE_I,
> > > SBI_EXT_RFENCE_REMOTE_FENCE_I,
> > > hart_mask, 0, 0, 0, 0, 0);
> > > }
> > > EXPORT_SYMBOL(sbi_remote_fence_i);
> > > @@ -255,7 +350,8 @@ void sbi_remote_sfence_vma(const unsigned
> > > long *hart_mask,
> > > unsigned long start,
> > > unsigned long size)
> > > {
> > > - __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
> > > + __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA,
> > > + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
> > > hart_mask, 0, start, size, 0, 0);
> > > }
> > > EXPORT_SYMBOL(sbi_remote_sfence_vma);
> > > @@ -276,11 +372,93 @@ void sbi_remote_sfence_vma_asid(const
> > > unsigned long *hart_mask,
> > > unsigned long size,
> > > unsigned long asid)
> > > {
> > > - __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
> > > + __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID,
> > > + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
> > > hart_mask, 0, start, size, asid, 0);
> > > }
> > > EXPORT_SYMBOL(sbi_remote_sfence_vma_asid);
> > >
> > > +/**
> > > + * sbi_remote_hfence_gvma() - Execute HFENCE.GVMA instructions
> > > on given remote
> > > + * harts for the specified guest physical
> > > address range.
> > > + * @hart_mask: A cpu mask containing all the target harts.
> > > + * @start: Start of the guest physical address
> > > + * @size: Total size of the guest physical address range.
> > > + *
> > > + * Return: None
> > > + */
> > > +int sbi_remote_hfence_gvma(const unsigned long *hart_mask,
> > > + unsigned long start,
> > > + unsigned long size)
> > > +{
> > > + return __sbi_rfence(SBI_EXT_RFENCE,
> > > SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> > > + hart_mask, 0, start, size, 0, 0);
> > > +}
> > > +EXPORT_SYMBOL_GPL(sbi_remote_hfence_gvma);
> > > +
> > > +/**
> > > + * sbi_remote_hfence_gvma_vmid() - Execute HFENCE.GVMA
> > > instructions on given
> > > + * remote harts for a guest physical address range belonging to
> > > a specific VMID.
> > > + *
> > > + * @hart_mask: A cpu mask containing all the target harts.
> > > + * @start: Start of the guest physical address
> > > + * @size: Total size of the guest physical address range.
> > > + * @vmid: The value of guest ID (VMID).
> > > + *
> > > + * Return: 0 if success, Error otherwise.
> > > + */
> > > +int sbi_remote_hfence_gvma_vmid(const unsigned long *hart_mask,
> > > + unsigned long
> > > start,
> > > + unsigned long size,
> > > + unsigned long vmid)
> > > +{
> > > + return __sbi_rfence(SBI_EXT_RFENCE,
> > > + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMI
> > > D,
> > > + hart_mask, 0, start, size, vmid, 0);
> > > +}
> > > +EXPORT_SYMBOL(sbi_remote_hfence_gvma_vmid);
> > > +
> > > +/**
> > > + * sbi_remote_hfence_vvma() - Execute HFENCE.VVMA instructions
> > > on given remote
> > > + * harts for the current guest virtual
> > > address range.
> > > + * @hart_mask: A cpu mask containing all the target harts.
> > > + * @start: Start of the current guest virtual address
> > > + * @size: Total size of the current guest virtual address range.
> > > + *
> > > + * Return: None
> > > + */
> > > +int sbi_remote_hfence_vvma(const unsigned long *hart_mask,
> > > + unsigned long start,
> > > + unsigned long size)
> > > +{
> > > + return __sbi_rfence(SBI_EXT_RFENCE,
> > > SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> > > + hart_mask, 0, start, size, 0, 0);
> > > +}
> > > +EXPORT_SYMBOL(sbi_remote_hfence_vvma);
> > > +
> > > +/**
> > > + * sbi_remote_hfence_vvma_asid() - Execute HFENCE.VVMA
> > > instructions on given
> > > + * remote harts for current guest virtual address range
> > > belonging to a specific
> > > + * ASID.
> > > + *
> > > + * @hart_mask: A cpu mask containing all the target harts.
> > > + * @start: Start of the current guest virtual address
> > > + * @size: Total size of the current guest virtual address range.
> > > + * @asid: The value of address space identifier (ASID).
> > > + *
> > > + * Return: None
> > > + */
> > > +int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
> > > + unsigned long
> > > start,
> > > + unsigned long size,
> > > + unsigned long asid)
> > > +{
> > > + return __sbi_rfence(SBI_EXT_RFENCE,
> > > + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASI
> > > D,
> > > + hart_mask, 0, start, size, asid, 0);
> > > +}
> > > +EXPORT_SYMBOL(sbi_remote_hfence_vvma_asid);
> > > +
> > > /**
> > > * sbi_probe_extension() - Check if an SBI extension ID is
> > > supported or not.
> > > * @extid: The extension ID to be probed.
> > > @@ -356,11 +534,27 @@ int __init sbi_init(void)
> > > if (!sbi_spec_is_0_1()) {
> > > pr_info("SBI implementation ID=0x%lx
> > > Version=0x%lx\n",
> > > sbi_get_firmware_id(),
> > > sbi_get_firmware_version());
> > > + if (sbi_probe_extension(SBI_EXT_TIME) > 0) {
> > > + __sbi_set_timer = __sbi_set_timer_v02;
> > > + pr_info("SBI v0.2 TIME extension
> > > detected\n");
> > > + } else
> > > + __sbi_set_timer =
> > > __sbi_set_timer_dummy_warn;
> > This should be:
> >
> > #if IS_ENABLED(RISCV_SBI_V01)
> > __sbi_rfence = __sbi_set_timer_v01;
> > #else
> > __sbi_rfence =
> > __sbi_set_timer_dummy_warn;
> > #endif
>
> Instead of this, just do the following:
> __sbi_rfence = __sbi_set_timer_v01;
>
> > > + if (sbi_probe_extension(SBI_EXT_IPI) > 0) {
> > > + __sbi_send_ipi = __sbi_send_ipi_v02;
> > > + pr_info("SBI v0.2 IPI extension
> > > detected\n");
> > > + } else
> > > + __sbi_send_ipi =
> > > __sbi_send_ipi_dummy_warn;
> > This should be:
> >
> > #if IS_ENABLED(RISCV_SBI_V01)
> > __sbi_rfence = __sbi_ipi_v01;
> > #else
> > __sbi_rfence = __sbi_send_ipi_dummy_warn;
> > #endif
>
> Instead of this, just do the following:
> __sbi_rfence = __sbi_ipi_v01;
>
> > > + if (sbi_probe_extension(SBI_EXT_RFENCE) > 0) {
> > > + __sbi_rfence = __sbi_rfence_v02;
> > > + pr_info("SBI v0.2 RFENCE extension
> > > detected\n");
> > > + } else
> > > + __sbi_rfence =
> > > __sbi_rfence_dummy_warn;
> > This should be:
> >
> > #if IS_ENABLED(RISCV_SBI_V01)
> > __sbi_rfence = __sbi_rfence_v01;
> > #else
> > __sbi_rfence = __sbi_rfence_dummy_warn;
> > #endif
>
> Instead of this, just do the following:
> __sbi_rfence = __sbi_rfence_v01;
> > > +
> > > + } else {
> > > + __sbi_set_timer = __sbi_set_timer_v01;
> > > + __sbi_send_ipi = __sbi_send_ipi_v01;
> > > + __sbi_rfence = __sbi_rfence_v01;
> >
> > This should be:
> >
> > #if IS_ENABLED(RISCV_SBI_V01)
> > __sbi_set_timer = __sbi_set_timer_v01;
> > __sbi_send_ipi = __sbi_send_ipi_v01;
> > __sbi_rfence = __sbi_rfence_v01;
> > #else
> > __sbi_set_timer = __sbi_set_timer_dummy_warn;
> > __sbi_send_ipi = __sbi_send_ipi_dummy_warn;
> > __sbi_rfence = __sbi_rfence_dummy_warn;
> > #endif
>
> This is not required.
>
Thanks for catching it. I will fix those in next version.
> > > }
> > >
> > > - __sbi_set_timer = __sbi_set_timer_v01;
> > > - __sbi_send_ipi = __sbi_send_ipi_v01;
> > > - __sbi_rfence = __sbi_rfence_v01;
> > > -
> > > return 0;
> > > }
> > > --
> > > 2.23.0
> > >
> >
> > Regards,
> > Anup
>
> Regards,
> Anup
--
Regards,
Atish
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v5 4/4] RISC-V: Implement new SBI v0.2 extensions
2019-11-26 19:05 ` [PATCH v5 4/4] RISC-V: Implement new SBI v0.2 extensions Atish Patra
2019-11-29 4:51 ` Anup Patel
@ 2019-12-04 18:52 ` Palmer Dabbelt
2019-12-04 22:04 ` Atish Patra
1 sibling, 1 reply; 15+ messages in thread
From: Palmer Dabbelt @ 2019-12-04 18:52 UTC (permalink / raw)
To: Atish Patra
Cc: aou, alexios.zavras, anup, linux-kernel, rppt, Atish Patra,
Paul Walmsley, linux-riscv, tglx, han_mao
On Tue, 26 Nov 2019 11:05:03 PST (-0800), Atish Patra wrote:
> Few v0.1 SBI calls are being replaced by new SBI calls that follows
> v0.2 calling convention. The specification changes can be found at
>
> riscv/riscv-sbi-doc#27
>
> Implement the replacement extensions and few additional new SBI
> function calls that makes way for a better SBI interface in future.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> arch/riscv/include/asm/sbi.h | 35 ++++++
> arch/riscv/kernel/sbi.c | 208 +++++++++++++++++++++++++++++++++--
> 2 files changed, 236 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index cc82ae63f8e0..54ba9eebec11 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -22,6 +22,9 @@ enum sbi_ext_id {
> SBI_EXT_0_1_SHUTDOWN = 0x8,
> #endif
> SBI_EXT_BASE = 0x10,
> + SBI_EXT_TIME = 0x54494D45,
> + SBI_EXT_IPI = 0x735049,
> + SBI_EXT_RFENCE = 0x52464E43,
> };
>
> enum sbi_ext_base_fid {
> @@ -34,6 +37,24 @@ enum sbi_ext_base_fid {
> SBI_BASE_GET_MIMPID,
> };
>
> +enum sbi_ext_time_fid {
> + SBI_EXT_TIME_SET_TIMER = 0,
> +};
> +
> +enum sbi_ext_ipi_fid {
> + SBI_EXT_IPI_SEND_IPI = 0,
> +};
> +
> +enum sbi_ext_rfence_fid {
> + SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
> + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
> + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
> + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
> + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
> +};
> +
> #define SBI_SPEC_VERSION_DEFAULT 0x1
> #define SBI_SPEC_VERSION_MAJOR_OFFSET 24
> #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
> @@ -74,6 +95,20 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> unsigned long start,
> unsigned long size,
> unsigned long asid);
> +int sbi_remote_hfence_gvma(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size);
> +int sbi_remote_hfence_gvma_vmid(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size,
> + unsigned long vmid);
> +int sbi_remote_hfence_vvma(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size);
> +int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size,
> + unsigned long asid);
> int sbi_probe_extension(long ext);
>
> /* Check if current SBI specification version is 0.1 or not */
> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> index ee710bfe0b0e..af3d5f8d8af7 100644
> --- a/arch/riscv/kernel/sbi.c
> +++ b/arch/riscv/kernel/sbi.c
> @@ -205,6 +205,101 @@ static int __sbi_rfence_v01(unsigned long ext, unsigned long fid,
> }
> #endif /* CONFIG_RISCV_SBI_V01 */
>
> +static void __sbi_set_timer_v02(uint64_t stime_value)
> +{
> +#if __riscv_xlen == 32
> + sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value,
> + stime_value >> 32, 0, 0, 0, 0);
> +#else
> + sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0,
> + 0, 0, 0, 0);
> +#endif
> +}
> +
> +static int __sbi_send_ipi_v02(const unsigned long *hart_mask)
> +{
> + unsigned long hmask_val;
> + struct sbiret ret = {0};
> + int result;
> +
> + if (!hart_mask)
> + hmask_val = *(cpumask_bits(cpu_online_mask));
> + else
> + hmask_val = *hart_mask;
> +
> + ret = sbi_ecall(SBI_EXT_IPI, SBI_EXT_IPI_SEND_IPI, hmask_val,
> + 0, 0, 0, 0, 0);
> + if (ret.error) {
> + pr_err("%s: failed with error [%d]\n", __func__,
> + sbi_err_map_linux_errno(ret.error));
> + result = ret.error;
> + } else
> + result = ret.value;
> +
> + return result;
> +}
> +
> +static int __sbi_rfence_v02(unsigned long extid, unsigned long fid,
> + const unsigned long *hart_mask,
> + unsigned long hbase, unsigned long start,
> + unsigned long size, unsigned long arg4,
> + unsigned long arg5)
> +{
> + unsigned long hmask_val;
> + struct sbiret ret = {0};
> + int result;
> + unsigned long ext = SBI_EXT_RFENCE;
> +
> + if (!hart_mask)
> + hmask_val = *(cpumask_bits(cpu_online_mask));
This needs to map from CPUs to harts. Even if we're frobbing all of the harts
they might still be different.
> + else
> + hmask_val = *hart_mask;
> +
> + switch (fid) {
> + case SBI_EXT_RFENCE_REMOTE_FENCE_I:
> + ret = sbi_ecall(ext, fid, hmask_val, 0, 0, 0, 0, 0);
> + break;
> + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA:
> + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> + size, 0, 0);
> + break;
> + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID:
> + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> + size, arg4, 0);
> + break;
> + /*TODO: Handle non zero hbase cases */
> + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA:
> + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> + size, 0, 0);
> + break;
> + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID:
> + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> + size, arg4, 0);
> + break;
> + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA:
> + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> + size, 0, 0);
> + break;
> + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID:
> + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> + size, arg4, 0);
> + break;
> + default:
> + pr_err("unknown function ID [%lu] for SBI extension [%lu]\n",
> + fid, ext);
> + result = -EINVAL;
> + }
> +
> + if (ret.error) {
> + pr_err("%s: failed with error [%d]\n", __func__,
> + sbi_err_map_linux_errno(ret.error));
> + result = ret.error;
> + } else
> + result = ret.value;
> +
> + return result;
> +}
> +
> /**
> * sbi_set_timer() - Program the timer for next timer event.
> * @stime_value: The value after which next timer event should fire.
> @@ -237,7 +332,7 @@ EXPORT_SYMBOL(sbi_send_ipi);
> */
> void sbi_remote_fence_i(const unsigned long *hart_mask)
> {
> - __sbi_rfence(SBI_EXT_0_1_REMOTE_FENCE_I, 0,
> + __sbi_rfence(SBI_EXT_0_1_REMOTE_FENCE_I, SBI_EXT_RFENCE_REMOTE_FENCE_I,
> hart_mask, 0, 0, 0, 0, 0);
> }
> EXPORT_SYMBOL(sbi_remote_fence_i);
> @@ -255,7 +350,8 @@ void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> unsigned long start,
> unsigned long size)
> {
> - __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
> + __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA,
> + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
> hart_mask, 0, start, size, 0, 0);
> }
> EXPORT_SYMBOL(sbi_remote_sfence_vma);
> @@ -276,11 +372,93 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> unsigned long size,
> unsigned long asid)
> {
> - __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
> + __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID,
> + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
> hart_mask, 0, start, size, asid, 0);
> }
> EXPORT_SYMBOL(sbi_remote_sfence_vma_asid);
>
> +/**
> + * sbi_remote_hfence_gvma() - Execute HFENCE.GVMA instructions on given remote
> + * harts for the specified guest physical address range.
> + * @hart_mask: A cpu mask containing all the target harts.
> + * @start: Start of the guest physical address
> + * @size: Total size of the guest physical address range.
> + *
> + * Return: None
> + */
> +int sbi_remote_hfence_gvma(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size)
> +{
> + return __sbi_rfence(SBI_EXT_RFENCE, SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> + hart_mask, 0, start, size, 0, 0);
> +}
> +EXPORT_SYMBOL_GPL(sbi_remote_hfence_gvma);
> +
> +/**
> + * sbi_remote_hfence_gvma_vmid() - Execute HFENCE.GVMA instructions on given
> + * remote harts for a guest physical address range belonging to a specific VMID.
> + *
> + * @hart_mask: A cpu mask containing all the target harts.
> + * @start: Start of the guest physical address
> + * @size: Total size of the guest physical address range.
> + * @vmid: The value of guest ID (VMID).
> + *
> + * Return: 0 if success, Error otherwise.
> + */
> +int sbi_remote_hfence_gvma_vmid(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size,
> + unsigned long vmid)
> +{
> + return __sbi_rfence(SBI_EXT_RFENCE,
> + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
> + hart_mask, 0, start, size, vmid, 0);
> +}
> +EXPORT_SYMBOL(sbi_remote_hfence_gvma_vmid);
> +
> +/**
> + * sbi_remote_hfence_vvma() - Execute HFENCE.VVMA instructions on given remote
> + * harts for the current guest virtual address range.
> + * @hart_mask: A cpu mask containing all the target harts.
> + * @start: Start of the current guest virtual address
> + * @size: Total size of the current guest virtual address range.
> + *
> + * Return: None
> + */
> +int sbi_remote_hfence_vvma(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size)
> +{
> + return __sbi_rfence(SBI_EXT_RFENCE, SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> + hart_mask, 0, start, size, 0, 0);
> +}
> +EXPORT_SYMBOL(sbi_remote_hfence_vvma);
> +
> +/**
> + * sbi_remote_hfence_vvma_asid() - Execute HFENCE.VVMA instructions on given
> + * remote harts for current guest virtual address range belonging to a specific
> + * ASID.
> + *
> + * @hart_mask: A cpu mask containing all the target harts.
> + * @start: Start of the current guest virtual address
> + * @size: Total size of the current guest virtual address range.
> + * @asid: The value of address space identifier (ASID).
> + *
> + * Return: None
> + */
> +int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size,
> + unsigned long asid)
> +{
> + return __sbi_rfence(SBI_EXT_RFENCE,
> + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
> + hart_mask, 0, start, size, asid, 0);
> +}
> +EXPORT_SYMBOL(sbi_remote_hfence_vvma_asid);
> +
> /**
> * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
> * @extid: The extension ID to be probed.
> @@ -356,11 +534,27 @@ int __init sbi_init(void)
> if (!sbi_spec_is_0_1()) {
> pr_info("SBI implementation ID=0x%lx Version=0x%lx\n",
> sbi_get_firmware_id(), sbi_get_firmware_version());
> + if (sbi_probe_extension(SBI_EXT_TIME) > 0) {
> + __sbi_set_timer = __sbi_set_timer_v02;
> + pr_info("SBI v0.2 TIME extension detected\n");
> + } else
> + __sbi_set_timer = __sbi_set_timer_dummy_warn;
> + if (sbi_probe_extension(SBI_EXT_IPI) > 0) {
> + __sbi_send_ipi = __sbi_send_ipi_v02;
> + pr_info("SBI v0.2 IPI extension detected\n");
> + } else
> + __sbi_send_ipi = __sbi_send_ipi_dummy_warn;
> + if (sbi_probe_extension(SBI_EXT_RFENCE) > 0) {
> + __sbi_rfence = __sbi_rfence_v02;
> + pr_info("SBI v0.2 RFENCE extension detected\n");
> + } else
> + __sbi_rfence = __sbi_rfence_dummy_warn;
> +
> + } else {
> + __sbi_set_timer = __sbi_set_timer_v01;
> + __sbi_send_ipi = __sbi_send_ipi_v01;
> + __sbi_rfence = __sbi_rfence_v01;
> }
>
> - __sbi_set_timer = __sbi_set_timer_v01;
> - __sbi_send_ipi = __sbi_send_ipi_v01;
> - __sbi_rfence = __sbi_rfence_v01;
> -
> return 0;
> }
This will have to change around when disentangling the legacy vs v0.1 stuff.
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v5 4/4] RISC-V: Implement new SBI v0.2 extensions
2019-12-04 18:52 ` Palmer Dabbelt
@ 2019-12-04 22:04 ` Atish Patra
0 siblings, 0 replies; 15+ messages in thread
From: Atish Patra @ 2019-12-04 22:04 UTC (permalink / raw)
To: palmerdabbelt
Cc: aou, anup, linux-kernel, rppt, alexios.zavras, paul.walmsley,
linux-riscv, tglx, han_mao
On Wed, 2019-12-04 at 10:52 -0800, Palmer Dabbelt wrote:
> On Tue, 26 Nov 2019 11:05:03 PST (-0800), Atish Patra wrote:
> > Few v0.1 SBI calls are being replaced by new SBI calls that follows
> > v0.2 calling convention. The specification changes can be found at
> >
> > riscv/riscv-sbi-doc#27
> >
> > Implement the replacement extensions and few additional new SBI
> > function calls that makes way for a better SBI interface in future.
> >
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > Reviewed-by: Anup Patel <anup@brainfault.org>
> > ---
> > arch/riscv/include/asm/sbi.h | 35 ++++++
> > arch/riscv/kernel/sbi.c | 208
> > +++++++++++++++++++++++++++++++++--
> > 2 files changed, 236 insertions(+), 7 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/sbi.h
> > b/arch/riscv/include/asm/sbi.h
> > index cc82ae63f8e0..54ba9eebec11 100644
> > --- a/arch/riscv/include/asm/sbi.h
> > +++ b/arch/riscv/include/asm/sbi.h
> > @@ -22,6 +22,9 @@ enum sbi_ext_id {
> > SBI_EXT_0_1_SHUTDOWN = 0x8,
> > #endif
> > SBI_EXT_BASE = 0x10,
> > + SBI_EXT_TIME = 0x54494D45,
> > + SBI_EXT_IPI = 0x735049,
> > + SBI_EXT_RFENCE = 0x52464E43,
> > };
> >
> > enum sbi_ext_base_fid {
> > @@ -34,6 +37,24 @@ enum sbi_ext_base_fid {
> > SBI_BASE_GET_MIMPID,
> > };
> >
> > +enum sbi_ext_time_fid {
> > + SBI_EXT_TIME_SET_TIMER = 0,
> > +};
> > +
> > +enum sbi_ext_ipi_fid {
> > + SBI_EXT_IPI_SEND_IPI = 0,
> > +};
> > +
> > +enum sbi_ext_rfence_fid {
> > + SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
> > + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
> > + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
> > + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> > + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
> > + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> > + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
> > +};
> > +
> > #define SBI_SPEC_VERSION_DEFAULT 0x1
> > #define SBI_SPEC_VERSION_MAJOR_OFFSET 24
> > #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
> > @@ -74,6 +95,20 @@ void sbi_remote_sfence_vma_asid(const unsigned
> > long *hart_mask,
> > unsigned long start,
> > unsigned long size,
> > unsigned long asid);
> > +int sbi_remote_hfence_gvma(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size);
> > +int sbi_remote_hfence_gvma_vmid(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size,
> > + unsigned long vmid);
> > +int sbi_remote_hfence_vvma(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size);
> > +int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size,
> > + unsigned long asid);
> > int sbi_probe_extension(long ext);
> >
> > /* Check if current SBI specification version is 0.1 or not */
> > diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> > index ee710bfe0b0e..af3d5f8d8af7 100644
> > --- a/arch/riscv/kernel/sbi.c
> > +++ b/arch/riscv/kernel/sbi.c
> > @@ -205,6 +205,101 @@ static int __sbi_rfence_v01(unsigned long
> > ext, unsigned long fid,
> > }
> > #endif /* CONFIG_RISCV_SBI_V01 */
> >
> > +static void __sbi_set_timer_v02(uint64_t stime_value)
> > +{
> > +#if __riscv_xlen == 32
> > + sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value,
> > + stime_value >> 32, 0, 0, 0, 0);
> > +#else
> > + sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0,
> > + 0, 0, 0, 0);
> > +#endif
> > +}
> > +
> > +static int __sbi_send_ipi_v02(const unsigned long *hart_mask)
> > +{
> > + unsigned long hmask_val;
> > + struct sbiret ret = {0};
> > + int result;
> > +
> > + if (!hart_mask)
> > + hmask_val = *(cpumask_bits(cpu_online_mask));
> > + else
> > + hmask_val = *hart_mask;
> > +
> > + ret = sbi_ecall(SBI_EXT_IPI, SBI_EXT_IPI_SEND_IPI, hmask_val,
> > + 0, 0, 0, 0, 0);
> > + if (ret.error) {
> > + pr_err("%s: failed with error [%d]\n", __func__,
> > + sbi_err_map_linux_errno(ret.error));
> > + result = ret.error;
> > + } else
> > + result = ret.value;
> > +
> > + return result;
> > +}
> > +
> > +static int __sbi_rfence_v02(unsigned long extid, unsigned long
> > fid,
> > + const unsigned long *hart_mask,
> > + unsigned long hbase, unsigned long start,
> > + unsigned long size, unsigned long arg4,
> > + unsigned long arg5)
> > +{
> > + unsigned long hmask_val;
> > + struct sbiret ret = {0};
> > + int result;
> > + unsigned long ext = SBI_EXT_RFENCE;
> > +
> > + if (!hart_mask)
> > + hmask_val = *(cpumask_bits(cpu_online_mask));
>
> This needs to map from CPUs to harts. Even if we're frobbing all of
> the harts
> they might still be different.
>
Yes. You are correct. I will fix this.
> > + else
> > + hmask_val = *hart_mask;
> > +
> > + switch (fid) {
> > + case SBI_EXT_RFENCE_REMOTE_FENCE_I:
> > + ret = sbi_ecall(ext, fid, hmask_val, 0, 0, 0, 0, 0);
> > + break;
> > + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA:
> > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > + size, 0, 0);
> > + break;
> > + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID:
> > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > + size, arg4, 0);
> > + break;
> > + /*TODO: Handle non zero hbase cases */
> > + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA:
> > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > + size, 0, 0);
> > + break;
> > + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID:
> > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > + size, arg4, 0);
> > + break;
> > + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA:
> > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > + size, 0, 0);
> > + break;
> > + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID:
> > + ret = sbi_ecall(ext, fid, hmask_val, 0, start,
> > + size, arg4, 0);
> > + break;
> > + default:
> > + pr_err("unknown function ID [%lu] for SBI extension
> > [%lu]\n",
> > + fid, ext);
> > + result = -EINVAL;
> > + }
> > +
> > + if (ret.error) {
> > + pr_err("%s: failed with error [%d]\n", __func__,
> > + sbi_err_map_linux_errno(ret.error));
> > + result = ret.error;
> > + } else
> > + result = ret.value;
> > +
> > + return result;
> > +}
> > +
> > /**
> > * sbi_set_timer() - Program the timer for next timer event.
> > * @stime_value: The value after which next timer event should
> > fire.
> > @@ -237,7 +332,7 @@ EXPORT_SYMBOL(sbi_send_ipi);
> > */
> > void sbi_remote_fence_i(const unsigned long *hart_mask)
> > {
> > - __sbi_rfence(SBI_EXT_0_1_REMOTE_FENCE_I, 0,
> > + __sbi_rfence(SBI_EXT_0_1_REMOTE_FENCE_I,
> > SBI_EXT_RFENCE_REMOTE_FENCE_I,
> > hart_mask, 0, 0, 0, 0, 0);
> > }
> > EXPORT_SYMBOL(sbi_remote_fence_i);
> > @@ -255,7 +350,8 @@ void sbi_remote_sfence_vma(const unsigned long
> > *hart_mask,
> > unsigned long start,
> > unsigned long size)
> > {
> > - __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
> > + __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA,
> > + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
> > hart_mask, 0, start, size, 0, 0);
> > }
> > EXPORT_SYMBOL(sbi_remote_sfence_vma);
> > @@ -276,11 +372,93 @@ void sbi_remote_sfence_vma_asid(const
> > unsigned long *hart_mask,
> > unsigned long size,
> > unsigned long asid)
> > {
> > - __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
> > + __sbi_rfence(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID,
> > + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
> > hart_mask, 0, start, size, asid, 0);
> > }
> > EXPORT_SYMBOL(sbi_remote_sfence_vma_asid);
> >
> > +/**
> > + * sbi_remote_hfence_gvma() - Execute HFENCE.GVMA instructions on
> > given remote
> > + * harts for the specified guest physical
> > address range.
> > + * @hart_mask: A cpu mask containing all the target harts.
> > + * @start: Start of the guest physical address
> > + * @size: Total size of the guest physical address range.
> > + *
> > + * Return: None
> > + */
> > +int sbi_remote_hfence_gvma(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size)
> > +{
> > + return __sbi_rfence(SBI_EXT_RFENCE,
> > SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> > + hart_mask, 0, start, size, 0, 0);
> > +}
> > +EXPORT_SYMBOL_GPL(sbi_remote_hfence_gvma);
> > +
> > +/**
> > + * sbi_remote_hfence_gvma_vmid() - Execute HFENCE.GVMA
> > instructions on given
> > + * remote harts for a guest physical address range belonging to a
> > specific VMID.
> > + *
> > + * @hart_mask: A cpu mask containing all the target harts.
> > + * @start: Start of the guest physical address
> > + * @size: Total size of the guest physical address range.
> > + * @vmid: The value of guest ID (VMID).
> > + *
> > + * Return: 0 if success, Error otherwise.
> > + */
> > +int sbi_remote_hfence_gvma_vmid(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size,
> > + unsigned long vmid)
> > +{
> > + return __sbi_rfence(SBI_EXT_RFENCE,
> > + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
> > + hart_mask, 0, start, size, vmid, 0);
> > +}
> > +EXPORT_SYMBOL(sbi_remote_hfence_gvma_vmid);
> > +
> > +/**
> > + * sbi_remote_hfence_vvma() - Execute HFENCE.VVMA instructions on
> > given remote
> > + * harts for the current guest virtual
> > address range.
> > + * @hart_mask: A cpu mask containing all the target harts.
> > + * @start: Start of the current guest virtual address
> > + * @size: Total size of the current guest virtual address range.
> > + *
> > + * Return: None
> > + */
> > +int sbi_remote_hfence_vvma(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size)
> > +{
> > + return __sbi_rfence(SBI_EXT_RFENCE,
> > SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> > + hart_mask, 0, start, size, 0, 0);
> > +}
> > +EXPORT_SYMBOL(sbi_remote_hfence_vvma);
> > +
> > +/**
> > + * sbi_remote_hfence_vvma_asid() - Execute HFENCE.VVMA
> > instructions on given
> > + * remote harts for current guest virtual address range belonging
> > to a specific
> > + * ASID.
> > + *
> > + * @hart_mask: A cpu mask containing all the target harts.
> > + * @start: Start of the current guest virtual address
> > + * @size: Total size of the current guest virtual address range.
> > + * @asid: The value of address space identifier (ASID).
> > + *
> > + * Return: None
> > + */
> > +int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size,
> > + unsigned long asid)
> > +{
> > + return __sbi_rfence(SBI_EXT_RFENCE,
> > + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
> > + hart_mask, 0, start, size, asid, 0);
> > +}
> > +EXPORT_SYMBOL(sbi_remote_hfence_vvma_asid);
> > +
> > /**
> > * sbi_probe_extension() - Check if an SBI extension ID is
> > supported or not.
> > * @extid: The extension ID to be probed.
> > @@ -356,11 +534,27 @@ int __init sbi_init(void)
> > if (!sbi_spec_is_0_1()) {
> > pr_info("SBI implementation ID=0x%lx Version=0x%lx\n",
> > sbi_get_firmware_id(),
> > sbi_get_firmware_version());
> > + if (sbi_probe_extension(SBI_EXT_TIME) > 0) {
> > + __sbi_set_timer = __sbi_set_timer_v02;
> > + pr_info("SBI v0.2 TIME extension detected\n");
> > + } else
> > + __sbi_set_timer = __sbi_set_timer_dummy_warn;
> > + if (sbi_probe_extension(SBI_EXT_IPI) > 0) {
> > + __sbi_send_ipi = __sbi_send_ipi_v02;
> > + pr_info("SBI v0.2 IPI extension detected\n");
> > + } else
> > + __sbi_send_ipi = __sbi_send_ipi_dummy_warn;
> > + if (sbi_probe_extension(SBI_EXT_RFENCE) > 0) {
> > + __sbi_rfence = __sbi_rfence_v02;
> > + pr_info("SBI v0.2 RFENCE extension
> > detected\n");
> > + } else
> > + __sbi_rfence = __sbi_rfence_dummy_warn;
> > +
> > + } else {
> > + __sbi_set_timer = __sbi_set_timer_v01;
> > + __sbi_send_ipi = __sbi_send_ipi_v01;
> > + __sbi_rfence = __sbi_rfence_v01;
> > }
> >
> > - __sbi_set_timer = __sbi_set_timer_v01;
> > - __sbi_send_ipi = __sbi_send_ipi_v01;
> > - __sbi_rfence = __sbi_rfence_v01;
> > -
> > return 0;
> > }
>
> This will have to change around when disentangling the legacy vs v0.1
> stuff.
--
Regards,
Atish
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v5 0/4] Add support for SBI v0.2
2019-11-26 19:04 [PATCH v5 0/4] Add support for SBI v0.2 Atish Patra
` (3 preceding siblings ...)
2019-11-26 19:05 ` [PATCH v5 4/4] RISC-V: Implement new SBI v0.2 extensions Atish Patra
@ 2019-12-04 18:56 ` Palmer Dabbelt
4 siblings, 0 replies; 15+ messages in thread
From: Palmer Dabbelt @ 2019-12-04 18:56 UTC (permalink / raw)
To: Atish Patra
Cc: aou, alexios.zavras, anup, linux-kernel, rppt, Atish Patra,
Paul Walmsley, linux-riscv, tglx, han_mao
On Tue, 26 Nov 2019 11:04:59 PST (-0800), Atish Patra wrote:
> The Supervisor Binary Interface(SBI) specification[1] now defines a
> base extension that provides extendability to add future extensions
> while maintaining backward compatibility with previous versions.
> The new version is defined as 0.2 and older version is marked as 0.1.
>
> This series adds support v0.2 and a unified calling convention
> implementation between 0.1 and 0.2. It also add other SBI v0.2
> functionality defined in [2]. The base support for SBI v0.2 is already
> available in OpenSBI v0.5. This series needs additional patches[3] in
> OpenSBI.
>
> Tested on both BBL, OpenSBI with/without the above patch series.
>
> [1] https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
> [2] https://github.com/riscv/riscv-sbi-doc/pull/27
> [3] http://lists.infradead.org/pipermail/opensbi/2019-November/000738.html
>
> Changes from v4->v5
> 1. Fixed few minor comments related to static & inline.
> 2. Make sure that every patch is boot tested individually.
>
> Changes from v3->v4.
> 1. Rebased on top of for-next.
> 2. Fixed issuses with checkpatch --strict.
> 3. Unfied all IPI/fence related functions.
> 4. Added Hfence related SBI calls.
> 5. Moved to function pointer based boot time switch between v01 and v02 calls.
> Changes from v2->v3.
> 1. Moved v0.1 extensions to a new config.
> 2. Added support for relacement extensions of v0.1 extensions.
>
> Changes from v1->v2
> 1. Removed the legacy calling convention.
> 2. Moved all SBI related calls to sbi.c.
> 3. Moved all SBI related macros to uapi.
>
> Atish Patra (4):
> RISC-V: Mark existing SBI as 0.1 SBI.
> RISC-V: Add basic support for SBI v0.2
> RISC-V: Introduce a new config for SBI v0.1
> RISC-V: Implement new SBI v0.2 extensions
>
> arch/riscv/Kconfig | 6 +
> arch/riscv/include/asm/sbi.h | 177 +++++++-----
> arch/riscv/kernel/Makefile | 1 +
> arch/riscv/kernel/sbi.c | 547 ++++++++++++++++++++++++++++++++++-
> arch/riscv/kernel/setup.c | 2 +
> 5 files changed, 660 insertions(+), 73 deletions(-)
There's a few issues with the implementation, but I think the bigger question
is what do to with the spec. The SBI stuff sort of snuck in to Linux without
actually having a proper spec written down, so I'm happy to just say "let's
take the 0.2 stuff as soon as it's frozen" as we're at least in a better spot
than with the legacy stuff. Nominally we'd need to wait for a ratified
specification here, which probably means a 1.0 specification, but that's a way
off and I don't want to just sit around on the legacy stuff.
^ permalink raw reply [flat|nested] 15+ messages in thread