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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=xlkirLsIZMObxpVgMysLgRaq8YNVzTc6KirQpgVXrl4=; b=ms01BsmlhmTwU6SQt43DJr+nnLMfWi6o2G2YDbyp/F5SwSSPe2ouNNK4hR0amBPOEH VVIMEkgdUDMy38c0d/oh9bgcvgRh0nYr1n38n+tldk9RrepPIeaJgvU+XEBZheT4pKKc jxD0IcovMRMIYGw9fsErLdrow7HTNyatmCcQM6PllXGHixSfCX8vusi3XkovYejhfWoU zP1LmVMENz/h4tijOjIe8bo55B+dRWUm1Xaqm7hUDbs6p/g3vxGQfXc2lxuXD1aDJWvu s7rYg4jLpQVVwdMObgzekNa48O5v9LdnOtQBmI6qETByVYQIJlbg0ptLXADpkMSU1zAO asCw== X-Gm-Message-State: AOAM530v9uGfzqKHC/UYg0vIpdcEMa7qO43+I8hWBiGgqKFllXUpsFmy RuBQEDoeeZ5bhg6mpL7bAY+3RJIDO9rwBXK19Nr1Wg== X-Google-Smtp-Source: ABdhPJxa/xVZEo4rcONrdXK7z4EBCafJE7t3pkJxGBiHDISKtOWNiYaOD0c0v3gOgqNI5AKRBTrN8tHGHJujsgatwnI= X-Received: by 2002:adf:de12:: with SMTP id b18mr16280822wrm.390.1593406386452; Sun, 28 Jun 2020 21:53:06 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Anup Patel Date: Mon, 29 Jun 2020 10:22:55 +0530 Message-ID: Subject: Re: [RFC PATCH 0/6] Support raw event and DT for perf on RISC-V To: Zong Li X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-riscv , Palmer Dabbelt , "linux-kernel@vger.kernel.org List" , Paul Walmsley Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Jun 29, 2020 at 8:49 AM Zong Li wrote: > > This patch set adds raw event support on RISC-V. In addition, we > introduce the DT mechanism to make our perf more generic and common. > > Currently, we set the hardware events by writing the mhpmeventN CSRs, it > would raise an illegal instruction exception and trap into m-mode to > emulate event selector CSRs access. It doesn't make sense because we > shouldn't write the m-mode CSRs in s-mode. Ideally, we should set event > selector through standard SBI call or the shadow CSRs of s-mode. We have > prepared a proposal of a new SBI extension, called "PMU SBI extension", > but we also discussing the feasibility of accessing these PMU CSRs on > s-mode at the same time, such as delegation mechanism, so I was > wondering if we could use SBI calls first and make the PMU SBI extension > as legacy when s-mode access mechanism is accepted by Foundation? or > keep the current situation to see what would happen in the future. > > This patch set also introduces the DT mechanism, we don't want to add too > much platform-dependency code in perf like other architectures, so we > put the mapping of generic hardware events to DT, then we can easy to > transfer generic hardware events to vendor's own hardware events without > any platfrom-dependency stuff in our perf. Please re-write this series to have RISC-V PMU driver as a regular platform driver as drivers/perf/riscv_pmu.c. The PMU related sources will have to be removed from arch/riscv. Based on implementation of final drivers/perf/riscv_pmu.c we will come-up with drivers/perf/riscv_sbi_pmu.c driver for SBI perf counters. Regards, Anup > > Zong Li (6): > dt-bindings: riscv: Add YAML documentation for PMU > riscv: dts: sifive: Add DT support for PMU > riscv: add definition of hpmcounter CSRs > riscv: perf: Add raw event support > riscv: perf: introduce DT mechanism > riscv: remove PMU menu of Kconfig > > .../devicetree/bindings/riscv/pmu.yaml | 59 +++ > arch/riscv/Kconfig | 13 - > arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 13 + > arch/riscv/include/asm/csr.h | 58 +++ > arch/riscv/include/asm/perf_event.h | 100 ++-- > arch/riscv/kernel/Makefile | 2 +- > arch/riscv/kernel/perf_event.c | 471 +++++++++++------- > 7 files changed, 471 insertions(+), 245 deletions(-) > create mode 100644 Documentation/devicetree/bindings/riscv/pmu.yaml > > -- > 2.27.0 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv