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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=EyjzXR8COdd1eoaRXFYjBLgXqmenG49ZI6sEr2gOrtw=; b=HhomJ8HocE+GW75iYjbm14SnCmKQoBtFTtuZSorfAJrnYt8slJlbD07kVhs5J+bKEJ 7IVar2XlSOtnfVD3g5PuTrQad8PtcoNILtiLz+E1wMwQsC0r60APh+BzNxGdcCwfPyIx a13q3zUjRNw4EoeM0hdFRRzNHOONHlS7pmr29+RdMAsQhDnBu9/woN1dB+NqVi0JRg/V A7yVOgI3o9d0yU37z3nsKmnypAP/SSA/wMnALdGxh5pHJSutQ2PaK6/ZTCyWXFRIQv5c Z8gHRfV15hjzt+2MlQQ28qIFigmv4nnAbs8x3I/3WpoiZB3Z7I9Lo0InhxVobjgI79KU nsKw== X-Gm-Message-State: APjAAAUedEe+Zp1LR7pR/iKeT7yhCJ2fboEsRILdbWGVo9MWLHA8Vgw8 VaNbzkHWTY5JcOsX1UEVfBAH0wKYT72SKdhayKi+Ow== X-Google-Smtp-Source: APXvYqy8JGDxg4Mr/pqYBdBQ3gHtmzQ+mvGy2inraq9v/RF0Hlgf/VdA+Rkzqv7LoaKDL2B0TlDYpBsMBqiwN3AWFQc= X-Received: by 2002:adf:fa12:: with SMTP id m18mr21869141wrr.309.1578978026945; Mon, 13 Jan 2020 21:00:26 -0800 (PST) MIME-Version: 1.0 References: <1578897500-23897-1-git-send-email-yash.shah@sifive.com> <1578897500-23897-3-git-send-email-yash.shah@sifive.com> In-Reply-To: <1578897500-23897-3-git-send-email-yash.shah@sifive.com> From: Anup Patel Date: Tue, 14 Jan 2020 10:30:16 +0530 Message-ID: Subject: Re: [PATCH v3 2/2] riscv: Add support to determine no. of L2 cache way enabled To: Yash Shah Content-Type: text/plain; charset="UTF-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200113_210029_258892_BFBC9CBE X-CRM114-Status: GOOD ( 17.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Albert Ou , Sachin Ghadi , Greg Kroah-Hartman , "linux-kernel@vger.kernel.org List" , Alexios Zavras , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , bp@suse.de, linux-riscv , Allison Randal Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Jan 13, 2020 at 12:09 PM Yash Shah wrote: > > In order to determine the number of L2 cache ways enabled at runtime, > implement a private attribute ("number_of_ways_enabled"). Reading this > attribute returns the number of enabled L2 cache ways at runtime. > > Using riscv_set_cacheinfo_ops() hook a custom function, that returns > this private attribute, to the generic ops structure which is used by > cache_get_priv_group() in cacheinfo framework. > > Signed-off-by: Yash Shah > --- > drivers/soc/sifive/sifive_l2_cache.c | 38 ++++++++++++++++++++++++++++++++++++ > include/soc/sifive/sifive_l2_cache.h | 2 ++ > 2 files changed, 40 insertions(+) > > diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c > index a506939..8741885 100644 > --- a/drivers/soc/sifive/sifive_l2_cache.c > +++ b/drivers/soc/sifive/sifive_l2_cache.c > @@ -9,6 +9,8 @@ > #include > #include > #include > +#include > +#include > #include > > #define SIFIVE_L2_DIRECCFIX_LOW 0x100 > @@ -31,6 +33,7 @@ > > static void __iomem *l2_base; > static int g_irq[SIFIVE_L2_MAX_ECCINTR]; > +static struct riscv_cacheinfo_ops l2_cache_ops; > > enum { > DIR_CORR = 0, > @@ -107,6 +110,38 @@ int unregister_sifive_l2_error_notifier(struct notifier_block *nb) > } > EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier); > > +int sifive_l2_largest_wayenabled(void) > +{ > + return readl(l2_base + SIFIVE_L2_WAYENABLE); > +} The sifine_l2_largest_wayenabled() is not called from anywhere else so make it static and rename it to l2_largest_wayenabled(). > + > +static ssize_t number_of_ways_enabled_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + return sprintf(buf, "%u\n", sifive_l2_largest_wayenabled()); > +} > + > +static DEVICE_ATTR_RO(number_of_ways_enabled); > + > +static struct attribute *priv_attrs[] = { > + &dev_attr_number_of_ways_enabled.attr, > + NULL, > +}; > + > +static const struct attribute_group priv_attr_group = { > + .attrs = priv_attrs, > +}; > + > +const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf) > +{ > + /* We want to use private group for L2 cache only */ > + if (this_leaf->level == 2) > + return &priv_attr_group; > + else > + return NULL; > +} > + > static irqreturn_t l2_int_handler(int irq, void *device) > { > unsigned int add_h, add_l; > @@ -170,6 +205,9 @@ static int __init sifive_l2_init(void) > > l2_config_read(); > > + l2_cache_ops.get_priv_group = l2_get_priv_group; > + riscv_set_cacheinfo_ops(&l2_cache_ops); > + > #ifdef CONFIG_DEBUG_FS > setup_sifive_debug(); > #endif > diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifive_l2_cache.h > index 92ade10..55feff5 100644 > --- a/include/soc/sifive/sifive_l2_cache.h > +++ b/include/soc/sifive/sifive_l2_cache.h > @@ -10,6 +10,8 @@ > extern int register_sifive_l2_error_notifier(struct notifier_block *nb); > extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb); > > +int sifive_l2_largest_wayenabled(void); > + You can drop the sifive_l2_largest_wayenabled() declaration from here. > #define SIFIVE_L2_ERR_TYPE_CE 0 > #define SIFIVE_L2_ERR_TYPE_UE 1 > > -- > 2.7.4 > Apart from above it looks good. Reviewed-by: Anup Patel Regards, Anup