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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=OnfX0OE0ma/Av42U9uoiSTKulXAJE+HJ9d0B8OOmxos=; b=eoM7BLJG/+eG/dY7POhsCEIa2UVPH58RvkQ+SnWgJqt1XeImTftt3DGaUs6t2SHMHD 8VnE0QPjdncXvHUO5K07fFHId6C1GV5YtXkootlo3pDzRTm7AnuCZH0Hjd/C5Wm4X1Pu 2K6lpGYRoRF0qTxpp7/tw79iKyAZct2yCidnnKfyVYYhUH9buoBsaLFYxGxbnyjxsRvd zdOqoRoYP5eDjo8UUfBYll1ztPV7g0MRz23jOZ0EgWd03pqLow9fqOVzWCYWAPXEEncu +OPfBOXyataxIPgtDtgJtiES5XmJGtbJvQpTJKmp7cms28B26uBdrTS2Dkuw048gdGHy z9fA== X-Gm-Message-State: ANhLgQ2wmZNaUlPniRjDgyUdK5aqaeZdpUy2X4eH8EBh4o1J26iUwZG6 N6+g9fNzsHwpG/un5KHAWRcR1IOZMDME73OB0VrxYA== X-Google-Smtp-Source: ADFU+vvmAe5q2S2uktbITom5JQ9VBVLvh1KAt20YhWxpacdHL4eK/daDkLZcSd9w2y56WpFTbk1b6CJ9SZ717v2JK/0= X-Received: by 2002:adf:f3c5:: with SMTP id g5mr7627562wrp.230.1585206239889; Thu, 26 Mar 2020 00:03:59 -0700 (PDT) MIME-Version: 1.0 References: <20200322110028.18279-1-alex@ghiti.fr> <20200322110028.18279-7-alex@ghiti.fr> In-Reply-To: <20200322110028.18279-7-alex@ghiti.fr> From: Anup Patel Date: Thu, 26 Mar 2020 12:33:48 +0530 Message-ID: Subject: Re: [RFC PATCH 6/7] dt-bindings: riscv: Remove "riscv, svXX" property from device-tree To: Alexandre Ghiti Content-Type: text/plain; charset="UTF-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200326_000401_356222_E2E44049 X-CRM114-Status: GOOD ( 12.72 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "linux-kernel@vger.kernel.org List" , Palmer Dabbelt , Zong Li , Paul Walmsley , linux-riscv , Christoph Hellwig Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org +Device tree mailing list On Sun, Mar 22, 2020 at 4:36 PM Alexandre Ghiti wrote: > > This property can not be used before virtual memory is set up > and then the distinction between sv39 and sv48 is done at runtime > using SATP csr property: this property is now useless, so remove it. > > Signed-off-by: Alexandre Ghiti > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 13 ------------- > 1 file changed, 13 deletions(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 04819ad379c2..12baabbac213 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -39,19 +39,6 @@ properties: > Identifies that the hart uses the RISC-V instruction set > and identifies the type of the hart. > > - mmu-type: > - allOf: > - - $ref: "/schemas/types.yaml#/definitions/string" > - - enum: > - - riscv,sv32 > - - riscv,sv39 > - - riscv,sv48 > - description: > - Identifies the MMU address translation mode used on this > - hart. These values originate from the RISC-V Privileged > - Specification document, available from > - https://riscv.org/specifications/ > - > riscv,isa: > allOf: > - $ref: "/schemas/types.yaml#/definitions/string" > -- > 2.20.1 > Looks good to me. Reviewed-by: Anup Patel Regards, Anup