From: Anup Patel <anup@brainfault.org>
To: Christoph Hellwig <hch@infradead.org>
Cc: Palmer Dabbelt <palmer@sifive.com>,
Anup Patel <Anup.Patel@wdc.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Atish Patra <Atish.Patra@wdc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Paul Walmsley <paul.walmsley@sifive.com>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>
Subject: Re: [PATCH v4 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/csr.h
Date: Thu, 25 Apr 2019 12:46:52 +0530 [thread overview]
Message-ID: <CAAhSdy36q1R8HQRG3kXDqj5JoJbO_drignvO7wCHJ3-6wkE5rw@mail.gmail.com> (raw)
In-Reply-To: <20190425055757.GA30545@infradead.org>
On Thu, Apr 25, 2019 at 11:28 AM Christoph Hellwig <hch@infradead.org> wrote:
>
> > +#ifdef CONFIG_64BIT
> > +#define SCAUSE_IRQ_FLAG _AC(0x8000000000000000, UL)
> > +#else
> > +#define SCAUSE_IRQ_FLAG _AC(0x80000000, UL)
> > +#endif
>
> Please keep the existing defintion that doesn't need an ifdef..
Sure, will do.
Regards,
Anup
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next prev parent reply other threads:[~2019-04-25 7:17 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-25 5:50 [PATCH v4 0/3] Allow accessing CSR using CSR number Anup Patel
2019-04-25 5:50 ` [PATCH v4 1/3] RISC-V: Use tabs to align macro values in asm/csr.h Anup Patel
2019-04-25 5:50 ` [PATCH v4 2/3] RISC-V: Add interrupt related SCAUSE defines " Anup Patel
2019-04-25 5:57 ` Christoph Hellwig
2019-04-25 7:16 ` Anup Patel [this message]
2019-04-25 8:01 ` Christoph Hellwig
2019-04-25 8:17 ` Anup Patel
2019-04-25 5:50 ` [PATCH v4 3/3] RISC-V: Access CSRs using CSR numbers Anup Patel
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