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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=g4Mto+u+o/GrqhpuJO5sk5R5bWRkMiGx0GZ7PDoZHhY=; b=pBOwaNz2bWkP/FNpLkdPGSpSffMU276GDmFlWs4BnY3yg+9SEci4pVBSNv5R5Z4PCG 0qMO/F5cJLz3ET368PAljyFaGkd2MtihDh8gnbD91wn/jq0BVQesBP4eWhbYhaCSe+q5 64q3W17RjqiIa0qN//CG38ejVsq8H4RztCddGydUE2PMY+kIhdLzOjDEfepUkhurca2e ZNW4r4sjmiqDRghlguHZ2QrIMYMvxwGmrpf0zcI/oacxdzOXI6K711duPnUYSNbVTQ1g 0cqrjcRisIlwvmOzl8bXzFoWwHvbZ8fUGxXlSe509Y6M8rT91cpJww1i5v83Ss+6VPar MKmA== X-Gm-Message-State: APjAAAXiUsY7FTByRROq8ZFeDrVTDUm09FXSX+Dlg/UE+5ivAtr+3RdL hAb+C0asI0KyHbPNn/y5APkhTE0xAEP9BOMYjjkASQ== X-Google-Smtp-Source: APXvYqxNQXi0Vk0popN48576tfFY9XromzfT2N02IGLgqdhJFMVPw6vXQpznv3nKE3ce9kACVusM9LL3MVE7mwSI0Mg= X-Received: by 2002:a1c:9d53:: with SMTP id g80mr7920551wme.103.1565151161058; Tue, 06 Aug 2019 21:12:41 -0700 (PDT) MIME-Version: 1.0 References: <20190803042723.7163-1-atish.patra@wdc.com> <20190803042723.7163-3-atish.patra@wdc.com> In-Reply-To: From: Anup Patel Date: Wed, 7 Aug 2019 09:42:29 +0530 Message-ID: Subject: Re: [PATCH v4 2/4] RISC-V: Add riscv_isa reprensenting ISA features common across CPUs To: Paul Walmsley X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190806_211243_279056_D2F7986B X-CRM114-Status: GOOD ( 14.27 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Albert Ou , Alan Kao , Greg Kroah-Hartman , Daniel Lezcano , "linux-kernel@vger.kernel.org List" , Johan Hovold , Atish Patra , Anup Patel , Rob Herring , Palmer Dabbelt , linux-riscv , Enrico Weigelt , Thomas Gleixner Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Aug 7, 2019 at 3:24 AM Paul Walmsley wrote: > > Hi Anup, Atish, > > On Fri, 2 Aug 2019, Atish Patra wrote: > > > From: Anup Patel > > > > This patch adds riscv_isa integer to represent ISA features common > > across all CPUs. The riscv_isa is not same as elf_hwcap because > > elf_hwcap will only have ISA features relevant for user-space apps > > whereas riscv_isa will have ISA features relevant to both kernel > > and user-space apps. > > > > One of the use case is KVM hypervisor where riscv_isa will be used > > to do following operations: > > > > 1. Check whether hypervisor extension is available > > 2. Find ISA features that need to be virtualized (e.g. floating > > point support, vector extension, etc.) > > > > Signed-off-by: Anup Patel > > Signed-off-by: Atish Patra > > Do you have any opinions on how this patch might change for the Z-prefix > extensions? This bitfield approach probably won't scale, and with the > EXPORT_SYMBOL(), it might be worth trying to put together a approach that > would work over the long term? Our plan is to use bitmap instead of bitfield and all Zxyz extensions will be assigned bit positions "27 + i" where "i" will be based on order in-which they are defined in RISC-V spec. In general, "i" is just a unique relative index (starting from 0). To summarize, the existing bitfield approach can be naturally extended using bitmap. We will update this patch accordingly. Regards, Anup _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv